Lines Matching full:iommu
20 #include <linux/amd-iommu.h>
26 #include <asm/iommu.h>
39 #include "../iommu-pages.h"
99 * structure describing one IOMMU in the ACPI table. Typically followed by one
119 * A device entry describing which devices a specific IOMMU translates and
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
198 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
238 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
240 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
243 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
245 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
248 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
252 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
254 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
276 struct amd_iommu *iommu; in get_global_efr() local
278 for_each_iommu(iommu) { in get_global_efr()
279 u64 tmp = iommu->features; in get_global_efr()
280 u64 tmp2 = iommu->features2; in get_global_efr()
282 if (list_is_first(&iommu->list, &amd_iommu_list)) { in get_global_efr()
293 …"Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", in get_global_efr()
295 iommu->index, iommu->pci_seg->id, in get_global_efr()
296 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), in get_global_efr()
297 PCI_FUNC(iommu->devid)); in get_global_efr()
311 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
315 iommu->features = h->efr_reg; in early_iommu_features_init()
316 iommu->features2 = h->efr_reg2; in early_iommu_features_init()
324 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
329 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
333 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
335 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
336 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
337 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
340 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
344 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
345 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
349 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
351 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
352 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
357 * AMD IOMMU MMIO register space handling functions
359 * These functions are used to program the IOMMU device registers in
365 * This function set the exclusion range in the IOMMU. DMA accesses to the
368 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
370 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
371 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
374 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
378 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
382 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
386 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
388 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
398 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
405 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
409 /* Programs the physical address of the device table into the IOMMU hardware */
410 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
413 u32 dev_table_size = iommu->pci_seg->dev_table_size; in iommu_set_device_table()
414 void *dev_table = (void *)get_dev_table(iommu); in iommu_set_device_table()
416 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
420 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
424 /* Generic functions to enable/disable certain features of the IOMMU. */
425 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
429 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
431 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
434 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
438 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
440 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
443 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
447 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
450 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
454 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
456 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
459 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
461 if (!iommu->mmio_base) in iommu_disable()
465 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
468 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
469 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
471 /* Disable IOMMU GA_LOG */ in iommu_disable()
472 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
473 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
475 /* Disable IOMMU PPR logging */ in iommu_disable()
476 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); in iommu_disable()
477 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); in iommu_disable()
479 /* Disable IOMMU hardware itself */ in iommu_disable()
480 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
483 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable()
487 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
502 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
504 if (iommu->mmio_base) in iommu_unmap_mmio_space()
505 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
506 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
527 * The functions below belong to the first pass of AMD IOMMU ACPI table
551 * After reading the highest device id from the IOMMU PCI capability header
646 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
670 /* Allocate per PCI segment IOMMU rlookup table. */
734 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
735 * write commands to that buffer later and the IOMMU will execute them
738 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
740 iommu->cmd_buf = iommu_alloc_pages(GFP_KERNEL, in alloc_command_buffer()
743 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
750 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, in amd_iommu_restart_log() argument
756 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
760 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); in amd_iommu_restart_log()
762 iommu_feature_disable(iommu, cntrl_log); in amd_iommu_restart_log()
763 iommu_feature_disable(iommu, cntrl_intr); in amd_iommu_restart_log()
765 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
767 iommu_feature_enable(iommu, cntrl_intr); in amd_iommu_restart_log()
768 iommu_feature_enable(iommu, cntrl_log); in amd_iommu_restart_log()
772 * This function restarts event logging in case the IOMMU experienced
775 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) in amd_iommu_restart_event_logging() argument
777 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, in amd_iommu_restart_event_logging()
783 * This function restarts event logging in case the IOMMU experienced
786 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) in amd_iommu_restart_ga_log() argument
788 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, in amd_iommu_restart_ga_log()
794 * This function resets the command buffer if the IOMMU stopped fetching
797 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
799 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
801 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
802 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
803 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
804 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
806 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
813 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
817 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
819 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
822 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
825 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
831 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
833 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
836 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
838 iommu_free_pages(iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
841 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, in iommu_alloc_4k_pages() argument
857 /* allocates the memory where the IOMMU will log its events to */
858 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
860 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, in alloc_event_buffer()
863 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
866 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
870 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
872 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
874 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
878 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
879 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
881 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
887 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
889 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
892 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
894 iommu_free_pages(iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
897 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
900 iommu_free_pages(iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
901 iommu_free_pages(iommu->ga_log_tail, get_order(8)); in free_ga_log()
906 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
911 if (!iommu->ga_log) in iommu_ga_log_enable()
914 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
915 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
917 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
919 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
921 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
922 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
925 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
926 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
929 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
941 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
946 iommu->ga_log = iommu_alloc_pages(GFP_KERNEL, get_order(GA_LOG_SIZE)); in iommu_init_ga_log()
947 if (!iommu->ga_log) in iommu_init_ga_log()
950 iommu->ga_log_tail = iommu_alloc_pages(GFP_KERNEL, get_order(8)); in iommu_init_ga_log()
951 if (!iommu->ga_log_tail) in iommu_init_ga_log()
956 free_ga_log(iommu); in iommu_init_ga_log()
961 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
963 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); in alloc_cwwb_sem()
965 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
968 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
970 if (iommu->cmd_sem) in free_cwwb_sem()
971 iommu_free_page((void *)iommu->cmd_sem); in free_cwwb_sem()
974 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
983 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
987 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
992 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
1005 static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) in set_dev_entry_bit() argument
1007 struct dev_table_entry *dev_table = get_dev_table(iommu); in set_dev_entry_bit()
1021 static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) in get_dev_entry_bit() argument
1023 struct dev_table_entry *dev_table = get_dev_table(iommu); in get_dev_entry_bit()
1028 static bool __copy_device_table(struct amd_iommu *iommu) in __copy_device_table() argument
1031 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in __copy_device_table()
1038 /* Each IOMMU use separate device table with the same size */ in __copy_device_table()
1039 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in __copy_device_table()
1040 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in __copy_device_table()
1045 pr_err("The device table size of IOMMU:%d is not expected!\n", in __copy_device_table()
1046 iommu->index); in __copy_device_table()
1118 struct amd_iommu *iommu; in copy_device_table() local
1131 for_each_iommu(iommu) { in copy_device_table()
1132 if (pci_seg->id != iommu->pci_seg->id) in copy_device_table()
1134 if (!__copy_device_table(iommu)) in copy_device_table()
1143 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) in amd_iommu_apply_erratum_63() argument
1147 sysmgt = get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | in amd_iommu_apply_erratum_63()
1148 (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); in amd_iommu_apply_erratum_63()
1151 set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); in amd_iommu_apply_erratum_63()
1158 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1162 set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS); in set_dev_entry_from_acpi()
1164 set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS); in set_dev_entry_from_acpi()
1166 set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); in set_dev_entry_from_acpi()
1168 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1); in set_dev_entry_from_acpi()
1170 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2); in set_dev_entry_from_acpi()
1172 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); in set_dev_entry_from_acpi()
1174 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); in set_dev_entry_from_acpi()
1176 amd_iommu_apply_erratum_63(iommu, devid); in set_dev_entry_from_acpi()
1178 amd_iommu_set_rlookup_table(iommu, devid); in set_dev_entry_from_acpi()
1289 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1292 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1301 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in init_iommu_from_acpi()
1315 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1341 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1353 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1383 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1384 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1416 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1444 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1447 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1483 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1549 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1631 static void __init free_sysfs(struct amd_iommu *iommu) in free_sysfs() argument
1633 if (iommu->iommu.dev) { in free_sysfs()
1634 iommu_device_unregister(&iommu->iommu); in free_sysfs()
1635 iommu_device_sysfs_remove(&iommu->iommu); in free_sysfs()
1639 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1641 free_sysfs(iommu); in free_iommu_one()
1642 free_cwwb_sem(iommu); in free_iommu_one()
1643 free_command_buffer(iommu); in free_iommu_one()
1644 free_event_buffer(iommu); in free_iommu_one()
1645 amd_iommu_free_ppr_log(iommu); in free_iommu_one()
1646 free_ga_log(iommu); in free_iommu_one()
1647 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1648 amd_iommu_iopf_uninit(iommu); in free_iommu_one()
1653 struct amd_iommu *iommu, *next; in free_iommu_all() local
1655 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1656 list_del(&iommu->list); in free_iommu_all()
1657 free_iommu_one(iommu); in free_iommu_all()
1658 kfree(iommu); in free_iommu_all()
1663 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1668 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1677 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1678 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1684 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1686 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1687 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1690 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1694 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1699 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1709 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1715 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1717 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1721 * This function glues the initialization function for one IOMMU
1723 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1725 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, in init_iommu_one() argument
1733 iommu->pci_seg = pci_seg; in init_iommu_one()
1735 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1736 atomic64_set(&iommu->cmd_sem_val, 0); in init_iommu_one()
1738 /* Add IOMMU to internal data structures */ in init_iommu_one()
1739 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1740 iommu->index = amd_iommus_present++; in init_iommu_one()
1742 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1747 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1748 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1751 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1753 iommu->devid = h->devid; in init_iommu_one()
1754 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1755 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1763 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1765 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1779 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1781 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1797 early_iommu_features_init(iommu, h); in init_iommu_one()
1804 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1805 iommu->mmio_phys_end); in init_iommu_one()
1806 if (!iommu->mmio_base) in init_iommu_one()
1809 return init_iommu_from_acpi(iommu, h); in init_iommu_one()
1812 static int __init init_iommu_one_late(struct amd_iommu *iommu) in init_iommu_one_late() argument
1816 if (alloc_cwwb_sem(iommu)) in init_iommu_one_late()
1819 if (alloc_command_buffer(iommu)) in init_iommu_one_late()
1822 if (alloc_event_buffer(iommu)) in init_iommu_one_late()
1825 iommu->int_enabled = false; in init_iommu_one_late()
1827 init_translation_status(iommu); in init_iommu_one_late()
1828 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one_late()
1829 iommu_disable(iommu); in init_iommu_one_late()
1830 clear_translation_pre_enabled(iommu); in init_iommu_one_late()
1831 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one_late()
1832 iommu->index); in init_iommu_one_late()
1835 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one_late()
1838 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one_late()
1844 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one_late()
1847 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; in init_iommu_one_late()
1879 * Iterates over all IOMMU entries in the ACPI table, allocates the
1880 * IOMMU structure and initializes it with init_iommu_one()
1886 struct amd_iommu *iommu; in init_iommu_all() local
1905 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1906 if (iommu == NULL) in init_iommu_all()
1909 ret = init_iommu_one(iommu, h, table); in init_iommu_all()
1921 /* Phase 3 : Enabling IOMMU features */ in init_iommu_all()
1922 for_each_iommu(iommu) { in init_iommu_all()
1923 ret = init_iommu_one_late(iommu); in init_iommu_all()
1931 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1934 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1941 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1943 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1944 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1945 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1954 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1955 return sysfs_emit(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1974 .name = "amd-iommu",
1985 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
1988 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
1992 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
1996 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
1997 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); in late_iommu_features_init()
2018 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
2020 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
2023 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2024 PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
2025 iommu->devid & 0xff); in iommu_init_pci()
2026 if (!iommu->dev) in iommu_init_pci()
2029 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
2030 iommu->dev->match_driver = false; in iommu_init_pci()
2032 /* ACPI _PRT won't have an IRQ for IOMMU */ in iommu_init_pci()
2033 iommu->dev->irq_managed = 1; in iommu_init_pci()
2035 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
2036 &iommu->cap); in iommu_init_pci()
2038 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
2041 late_iommu_features_init(iommu); in iommu_init_pci()
2048 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; in iommu_init_pci()
2050 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); in iommu_init_pci()
2059 iommu_enable_gt(iommu); in iommu_init_pci()
2062 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) in iommu_init_pci()
2065 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { in iommu_init_pci()
2071 init_iommu_perf_ctr(iommu); in iommu_init_pci()
2081 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
2084 iommu->root_pdev = in iommu_init_pci()
2085 pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2086 iommu->dev->bus->number, in iommu_init_pci()
2094 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
2095 &iommu->stored_addr_lo); in iommu_init_pci()
2096 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
2097 &iommu->stored_addr_hi); in iommu_init_pci()
2100 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
2104 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
2107 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
2110 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
2111 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
2113 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
2114 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
2119 * Allocate per IOMMU IOPF queue here so that in attach device path, in iommu_init_pci()
2123 ret = amd_iommu_iopf_init(iommu); in iommu_init_pci()
2128 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); in iommu_init_pci()
2130 return pci_enable_device(iommu->dev); in iommu_init_pci()
2171 struct amd_iommu *iommu; in amd_iommu_init_pci() local
2175 for_each_iommu(iommu) { in amd_iommu_init_pci()
2176 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
2178 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", in amd_iommu_init_pci()
2179 iommu->index, ret); in amd_iommu_init_pci()
2183 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
2199 for_each_iommu(iommu) in amd_iommu_init_pci()
2200 amd_iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
2217 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
2221 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
2225 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
2229 iommu); in iommu_setup_msi()
2232 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2301 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_unmask_irq() local
2311 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); in intcapxt_unmask_irq()
2316 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_mask_irq() local
2318 writeq(0, iommu->mmio_base + irqd->hwirq); in intcapxt_mask_irq()
2340 .name = "IOMMU-MSI",
2381 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, in __iommu_setup_intcapxt() argument
2387 int node = dev_to_node(&iommu->dev->dev); in __iommu_setup_intcapxt()
2395 info.data = iommu; in __iommu_setup_intcapxt()
2405 thread_fn, 0, devname, iommu); in __iommu_setup_intcapxt()
2415 static int iommu_setup_intcapxt(struct amd_iommu *iommu) in iommu_setup_intcapxt() argument
2419 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), in iommu_setup_intcapxt()
2420 "AMD-Vi%d-Evt", iommu->index); in iommu_setup_intcapxt()
2421 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, in iommu_setup_intcapxt()
2427 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), in iommu_setup_intcapxt()
2428 "AMD-Vi%d-PPR", iommu->index); in iommu_setup_intcapxt()
2429 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, in iommu_setup_intcapxt()
2436 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), in iommu_setup_intcapxt()
2437 "AMD-Vi%d-GA", iommu->index); in iommu_setup_intcapxt()
2438 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, in iommu_setup_intcapxt()
2446 static int iommu_init_irq(struct amd_iommu *iommu) in iommu_init_irq() argument
2450 if (iommu->int_enabled) in iommu_init_irq()
2454 ret = iommu_setup_intcapxt(iommu); in iommu_init_irq()
2455 else if (iommu->dev->msi_cap) in iommu_init_irq()
2456 ret = iommu_setup_msi(iommu); in iommu_init_irq()
2463 iommu->int_enabled = true; in iommu_init_irq()
2467 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_irq()
2469 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_irq()
2625 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2627 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2628 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2629 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2631 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2632 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2633 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2635 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2636 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2637 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2639 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2640 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2641 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2644 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2646 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2649 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2652 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2656 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2658 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2659 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2663 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2671 /* Enable the iommu */ in iommu_apply_resume_quirks()
2675 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2676 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2677 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2678 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2679 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2684 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2688 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2691 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2692 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2695 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2701 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2702 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2705 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2711 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) in iommu_disable_irtcachedis() argument
2713 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable_irtcachedis()
2716 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) in iommu_enable_irtcachedis() argument
2728 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); in iommu_enable_irtcachedis()
2729 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_enable_irtcachedis()
2732 iommu->irtcachedis_enabled = true; in iommu_enable_irtcachedis()
2733 pr_info("iommu%d (%#06x) : IRT cache is %s\n", in iommu_enable_irtcachedis()
2734 iommu->index, iommu->devid, in iommu_enable_irtcachedis()
2735 iommu->irtcachedis_enabled ? "disabled" : "enabled"); in iommu_enable_irtcachedis()
2738 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2740 iommu_disable(iommu); in early_enable_iommu()
2741 iommu_init_flags(iommu); in early_enable_iommu()
2742 iommu_set_device_table(iommu); in early_enable_iommu()
2743 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2744 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2745 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2746 iommu_enable_gt(iommu); in early_enable_iommu()
2747 iommu_enable_ga(iommu); in early_enable_iommu()
2748 iommu_enable_xt(iommu); in early_enable_iommu()
2749 iommu_enable_irtcachedis(iommu); in early_enable_iommu()
2750 iommu_enable(iommu); in early_enable_iommu()
2751 amd_iommu_flush_all_caches(iommu); in early_enable_iommu()
2764 struct amd_iommu *iommu; in early_enable_iommus() local
2784 for_each_iommu(iommu) { in early_enable_iommus()
2785 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2786 early_enable_iommu(iommu); in early_enable_iommus()
2797 for_each_iommu(iommu) { in early_enable_iommus()
2798 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2799 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2800 iommu_disable_irtcachedis(iommu); in early_enable_iommus()
2801 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2802 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2803 iommu_enable_ga(iommu); in early_enable_iommus()
2804 iommu_enable_xt(iommu); in early_enable_iommus()
2805 iommu_enable_irtcachedis(iommu); in early_enable_iommus()
2806 iommu_set_device_table(iommu); in early_enable_iommus()
2807 amd_iommu_flush_all_caches(iommu); in early_enable_iommus()
2814 struct amd_iommu *iommu; in enable_iommus_ppr() local
2819 for_each_iommu(iommu) in enable_iommus_ppr()
2820 amd_iommu_enable_ppr_log(iommu); in enable_iommus_ppr()
2827 struct amd_iommu *iommu; in enable_iommus_vapic() local
2829 for_each_iommu(iommu) { in enable_iommus_vapic()
2834 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2838 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in enable_iommus_vapic()
2839 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in enable_iommus_vapic()
2846 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2870 for_each_iommu(iommu) { in enable_iommus_vapic()
2871 if (iommu_init_ga_log(iommu) || in enable_iommus_vapic()
2872 iommu_ga_log_enable(iommu)) in enable_iommus_vapic()
2875 iommu_feature_enable(iommu, CONTROL_GAM_EN); in enable_iommus_vapic()
2877 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); in enable_iommus_vapic()
2892 struct amd_iommu *iommu; in disable_iommus() local
2894 for_each_iommu(iommu) in disable_iommus()
2895 iommu_disable(iommu); in disable_iommus()
2910 struct amd_iommu *iommu; in amd_iommu_resume() local
2912 for_each_iommu(iommu) in amd_iommu_resume()
2913 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
3010 * This is the hardware init function for AMD IOMMU in the system.
3014 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
3141 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
3144 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
3145 ret = iommu_init_irq(iommu); in amd_iommu_enable_interrupts()
3181 /* Don't use IOMMU if there is Stoney Ridge graphics */ in detect_ivrs()
3187 pr_info("Disable IOMMU on Stoney Ridge\n"); in detect_ivrs()
3205 * The SNP support requires that IOMMU must be enabled, and is in iommu_snp_enable()
3209 pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n"); in iommu_snp_enable()
3214 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); in iommu_snp_enable()
3220 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); in iommu_snp_enable()
3224 pr_info("IOMMU SNP support enabled.\n"); in iommu_snp_enable()
3234 * AMD IOMMU Initialization State Machine
3298 struct amd_iommu *iommu; in state_next() local
3304 for_each_iommu(iommu) in state_next()
3305 amd_iommu_flush_all_caches(iommu); in state_next()
3374 * This is the core init function for AMD IOMMU hardware in the system.
3380 struct amd_iommu *iommu; in amd_iommu_init() local
3387 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
3394 for_each_iommu(iommu) in amd_iommu_init()
3395 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
3414 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
3421 * Early detect code. This code runs at IOMMU detection time in the DMA
3442 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
3449 * Parsing functions for the AMD IOMMU specific kernel command line
3483 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); in parse_amd_iommu_options()
3672 /* CPU page table size should match IOMMU guest page table size */ in amd_iommu_pasid_supported()
3688 struct amd_iommu *iommu; in get_amd_iommu() local
3690 for_each_iommu(iommu) in get_amd_iommu()
3692 return iommu; in get_amd_iommu()
3698 * IOMMU EFR Performance Counter support functionality. This code allows
3699 * access to the IOMMU PC functionality.
3705 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3707 if (iommu) in amd_iommu_pc_get_max_banks()
3708 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3720 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3722 if (iommu) in amd_iommu_pc_get_max_counters()
3723 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3728 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3734 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3738 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3739 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3745 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3746 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3754 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3755 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3757 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3759 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3766 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3768 if (!iommu) in amd_iommu_pc_get_reg()
3771 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3774 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3776 if (!iommu) in amd_iommu_pc_set_reg()
3779 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()
3797 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); in iommu_page_make_shared()
3802 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); in iommu_page_make_shared()
3811 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", in iommu_page_make_shared()
3840 struct amd_iommu *iommu; in amd_iommu_snp_disable() local
3846 for_each_iommu(iommu) { in amd_iommu_snp_disable()
3847 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); in amd_iommu_snp_disable()
3851 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); in amd_iommu_snp_disable()
3855 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); in amd_iommu_snp_disable()