Lines Matching full:iommu
27 #include "iommu.h"
28 #include "../dma-iommu.h"
30 #include "../iommu-pages.h"
120 * Looks up an IOMMU-probed device using its source ID.
126 * released by the iommu subsystem after being returned. The caller
130 struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid) in device_rbtree_find() argument
136 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_find()
137 node = rb_find(&rid, &iommu->device_rbtree, device_rid_cmp_key); in device_rbtree_find()
140 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_find()
145 static int device_rbtree_insert(struct intel_iommu *iommu, in device_rbtree_insert() argument
151 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_insert()
152 curr = rb_find_add(&info->node, &iommu->device_rbtree, device_rid_cmp); in device_rbtree_insert()
153 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_insert()
162 struct intel_iommu *iommu = info->iommu; in device_rbtree_remove() local
165 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_remove()
166 rb_erase(&info->node, &iommu->device_rbtree); in device_rbtree_remove()
167 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_remove()
191 struct intel_iommu *iommu; /* the corresponding iommu */ member
221 static bool translation_pre_enabled(struct intel_iommu *iommu) in translation_pre_enabled() argument
223 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
226 static void clear_translation_pre_enabled(struct intel_iommu *iommu) in clear_translation_pre_enabled() argument
228 iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
231 static void init_translation_status(struct intel_iommu *iommu) in init_translation_status() argument
235 gsts = readl(iommu->reg + DMAR_GSTS_REG); in init_translation_status()
237 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
248 pr_info("IOMMU enabled\n"); in intel_iommu_setup()
252 pr_info("IOMMU disabled\n"); in intel_iommu_setup()
257 pr_warn("intel_iommu=forcedac deprecated; use iommu.forcedac instead\n"); in intel_iommu_setup()
260 pr_warn("intel_iommu=strict deprecated; use iommu.strict=1 instead\n"); in intel_iommu_setup()
272 pr_info("Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n"); in intel_iommu_setup()
295 * Calculate the Supported Adjusted Guest Address Widths of an IOMMU.
299 static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu) in __iommu_calculate_sagaw() argument
303 fl_sagaw = BIT(2) | (cap_fl5lp_support(iommu->cap) ? BIT(3) : 0); in __iommu_calculate_sagaw()
304 sl_sagaw = cap_sagaw(iommu->cap); in __iommu_calculate_sagaw()
307 if (!sm_supported(iommu) || !ecap_flts(iommu->ecap)) in __iommu_calculate_sagaw()
311 if (!ecap_slts(iommu->ecap)) in __iommu_calculate_sagaw()
317 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) in __iommu_calculate_agaw() argument
322 sagaw = __iommu_calculate_sagaw(iommu); in __iommu_calculate_agaw()
332 * Calculate max SAGAW for each iommu.
334 int iommu_calculate_max_sagaw(struct intel_iommu *iommu) in iommu_calculate_max_sagaw() argument
336 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); in iommu_calculate_max_sagaw()
340 * calculate agaw for each iommu.
344 int iommu_calculate_agaw(struct intel_iommu *iommu) in iommu_calculate_agaw() argument
346 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); in iommu_calculate_agaw()
349 static bool iommu_paging_structure_coherency(struct intel_iommu *iommu) in iommu_paging_structure_coherency() argument
351 return sm_supported(iommu) ? in iommu_paging_structure_coherency()
352 ecap_smpwc(iommu->ecap) : ecap_coherent(iommu->ecap); in iommu_paging_structure_coherency()
359 struct intel_iommu *iommu; in domain_update_iommu_coherency() local
366 if (!iommu_paging_structure_coherency(info->iommu)) { in domain_update_iommu_coherency()
376 for_each_active_iommu(iommu, drhd) { in domain_update_iommu_coherency()
377 if (!iommu_paging_structure_coherency(iommu)) { in domain_update_iommu_coherency()
389 struct intel_iommu *iommu; in domain_update_iommu_superpage() local
397 for_each_active_iommu(iommu, drhd) { in domain_update_iommu_superpage()
398 if (iommu != skip) { in domain_update_iommu_superpage()
400 if (!cap_fl1gp_support(iommu->cap)) in domain_update_iommu_superpage()
403 mask &= cap_super_page_val(iommu->cap); in domain_update_iommu_superpage()
483 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, in iommu_context_addr() argument
486 struct root_entry *root = &iommu->root_entry[bus]; in iommu_context_addr()
494 if (!alloc && context_copied(iommu, bus, devfn)) in iommu_context_addr()
498 if (sm_supported(iommu)) { in iommu_context_addr()
512 context = iommu_alloc_page_node(iommu->node, GFP_ATOMIC); in iommu_context_addr()
516 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); in iommu_context_addr()
519 __iommu_flush_cache(iommu, entry, sizeof(*entry)); in iommu_context_addr()
557 /* We know that this device on this chipset has its own IOMMU. in quirk_ioat_snb_local_iommu()
558 * If we find it under a different IOMMU, then the BIOS is lying in quirk_ioat_snb_local_iommu()
559 * to us. Hope that the IOMMU for this device is actually in quirk_ioat_snb_local_iommu()
570 /* we know that the this iommu should be at offset 0xa000 from vtbar */ in quirk_ioat_snb_local_iommu()
581 static bool iommu_is_dummy(struct intel_iommu *iommu, struct device *dev) in iommu_is_dummy() argument
583 if (!iommu || iommu->drhd->ignored) in iommu_is_dummy()
602 struct intel_iommu *iommu; in device_lookup_iommu() local
616 * the PF instead to find the IOMMU. */ in device_lookup_iommu()
624 for_each_iommu(iommu, drhd) { in device_lookup_iommu()
632 * which we used for the IOMMU lookup. Strictly speaking in device_lookup_iommu()
658 iommu = NULL; in device_lookup_iommu()
660 if (iommu_is_dummy(iommu, dev)) in device_lookup_iommu()
661 iommu = NULL; in device_lookup_iommu()
665 return iommu; in device_lookup_iommu()
675 static void free_context_table(struct intel_iommu *iommu) in free_context_table() argument
680 if (!iommu->root_entry) in free_context_table()
684 context = iommu_context_addr(iommu, i, 0, 0); in free_context_table()
688 if (!sm_supported(iommu)) in free_context_table()
691 context = iommu_context_addr(iommu, i, 0x80, 0); in free_context_table()
696 iommu_free_page(iommu->root_entry); in free_context_table()
697 iommu->root_entry = NULL; in free_context_table()
701 static void pgtable_walk(struct intel_iommu *iommu, unsigned long pfn, in pgtable_walk() argument
725 void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, in dmar_fault_dump_ptes() argument
737 pr_info("Dump %s table entries for IOVA 0x%llx\n", iommu->name, addr); in dmar_fault_dump_ptes()
740 rt_entry = &iommu->root_entry[bus]; in dmar_fault_dump_ptes()
746 if (sm_supported(iommu)) in dmar_fault_dump_ptes()
753 ctx_entry = iommu_context_addr(iommu, bus, devfn, 0); in dmar_fault_dump_ptes()
763 if (!sm_supported(iommu)) { in dmar_fault_dump_ptes()
803 pgtable_walk(iommu, addr >> VTD_PAGE_SHIFT, bus, devfn, pgtable, level); in dmar_fault_dump_ptes()
816 /* Address beyond IOMMU's addressing capabilities. */ in pfn_to_dma_pte()
1059 /* We can't just free the pages because the IOMMU may still be walking
1081 /* iommu handling */
1082 static int iommu_alloc_root_entry(struct intel_iommu *iommu) in iommu_alloc_root_entry() argument
1086 root = iommu_alloc_page_node(iommu->node, GFP_ATOMIC); in iommu_alloc_root_entry()
1089 iommu->name); in iommu_alloc_root_entry()
1093 __iommu_flush_cache(iommu, root, ROOT_SIZE); in iommu_alloc_root_entry()
1094 iommu->root_entry = root; in iommu_alloc_root_entry()
1099 static void iommu_set_root_entry(struct intel_iommu *iommu) in iommu_set_root_entry() argument
1105 addr = virt_to_phys(iommu->root_entry); in iommu_set_root_entry()
1106 if (sm_supported(iommu)) in iommu_set_root_entry()
1109 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_set_root_entry()
1110 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); in iommu_set_root_entry()
1112 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); in iommu_set_root_entry()
1115 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_set_root_entry()
1118 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_set_root_entry()
1124 if (cap_esrtps(iommu->cap)) in iommu_set_root_entry()
1127 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); in iommu_set_root_entry()
1128 if (sm_supported(iommu)) in iommu_set_root_entry()
1129 qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0); in iommu_set_root_entry()
1130 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); in iommu_set_root_entry()
1133 void iommu_flush_write_buffer(struct intel_iommu *iommu) in iommu_flush_write_buffer() argument
1138 if (!rwbf_quirk && !cap_rwbf(iommu->cap)) in iommu_flush_write_buffer()
1141 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_flush_write_buffer()
1142 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); in iommu_flush_write_buffer()
1145 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_flush_write_buffer()
1148 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_flush_write_buffer()
1152 static void __iommu_flush_context(struct intel_iommu *iommu, in __iommu_flush_context() argument
1172 iommu->name, type); in __iommu_flush_context()
1177 raw_spin_lock_irqsave(&iommu->register_lock, flag); in __iommu_flush_context()
1178 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); in __iommu_flush_context()
1181 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, in __iommu_flush_context()
1184 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in __iommu_flush_context()
1187 void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, in __iommu_flush_iotlb() argument
1190 int tlb_offset = ecap_iotlb_offset(iommu->ecap); in __iommu_flush_iotlb()
1209 iommu->name, type); in __iommu_flush_iotlb()
1213 if (cap_write_drain(iommu->cap)) in __iommu_flush_iotlb()
1216 raw_spin_lock_irqsave(&iommu->register_lock, flag); in __iommu_flush_iotlb()
1219 dmar_writeq(iommu->reg + tlb_offset, val_iva); in __iommu_flush_iotlb()
1220 dmar_writeq(iommu->reg + tlb_offset + 8, val); in __iommu_flush_iotlb()
1223 IOMMU_WAIT_OP(iommu, tlb_offset + 8, in __iommu_flush_iotlb()
1226 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in __iommu_flush_iotlb()
1239 struct intel_iommu *iommu, u8 bus, u8 devfn) in domain_lookup_dev_info() argument
1246 if (info->iommu == iommu && info->bus == bus && in domain_lookup_dev_info()
1308 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) in iommu_disable_protect_mem_regions() argument
1313 if (!cap_plmr(iommu->cap) && !cap_phmr(iommu->cap)) in iommu_disable_protect_mem_regions()
1316 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_disable_protect_mem_regions()
1317 pmen = readl(iommu->reg + DMAR_PMEN_REG); in iommu_disable_protect_mem_regions()
1319 writel(pmen, iommu->reg + DMAR_PMEN_REG); in iommu_disable_protect_mem_regions()
1322 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, in iommu_disable_protect_mem_regions()
1325 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_disable_protect_mem_regions()
1328 static void iommu_enable_translation(struct intel_iommu *iommu) in iommu_enable_translation() argument
1333 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_enable_translation()
1334 iommu->gcmd |= DMA_GCMD_TE; in iommu_enable_translation()
1335 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_enable_translation()
1338 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_enable_translation()
1341 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_enable_translation()
1344 static void iommu_disable_translation(struct intel_iommu *iommu) in iommu_disable_translation() argument
1349 if (iommu_skip_te_disable && iommu->drhd->gfx_dedicated && in iommu_disable_translation()
1350 (cap_read_drain(iommu->cap) || cap_write_drain(iommu->cap))) in iommu_disable_translation()
1353 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_disable_translation()
1354 iommu->gcmd &= ~DMA_GCMD_TE; in iommu_disable_translation()
1355 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_disable_translation()
1358 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_disable_translation()
1361 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_disable_translation()
1364 static int iommu_init_domains(struct intel_iommu *iommu) in iommu_init_domains() argument
1368 ndomains = cap_ndoms(iommu->cap); in iommu_init_domains()
1370 iommu->name, ndomains); in iommu_init_domains()
1372 spin_lock_init(&iommu->lock); in iommu_init_domains()
1374 iommu->domain_ids = bitmap_zalloc(ndomains, GFP_KERNEL); in iommu_init_domains()
1375 if (!iommu->domain_ids) in iommu_init_domains()
1384 set_bit(0, iommu->domain_ids); in iommu_init_domains()
1394 set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); in iommu_init_domains()
1399 static void disable_dmar_iommu(struct intel_iommu *iommu) in disable_dmar_iommu() argument
1401 if (!iommu->domain_ids) in disable_dmar_iommu()
1405 * All iommu domains must have been detached from the devices, in disable_dmar_iommu()
1408 if (WARN_ON(bitmap_weight(iommu->domain_ids, cap_ndoms(iommu->cap)) in disable_dmar_iommu()
1412 if (iommu->gcmd & DMA_GCMD_TE) in disable_dmar_iommu()
1413 iommu_disable_translation(iommu); in disable_dmar_iommu()
1416 static void free_dmar_iommu(struct intel_iommu *iommu) in free_dmar_iommu() argument
1418 if (iommu->domain_ids) { in free_dmar_iommu()
1419 bitmap_free(iommu->domain_ids); in free_dmar_iommu()
1420 iommu->domain_ids = NULL; in free_dmar_iommu()
1423 if (iommu->copied_tables) { in free_dmar_iommu()
1424 bitmap_free(iommu->copied_tables); in free_dmar_iommu()
1425 iommu->copied_tables = NULL; in free_dmar_iommu()
1429 free_context_table(iommu); in free_dmar_iommu()
1432 if (pasid_supported(iommu)) { in free_dmar_iommu()
1433 if (ecap_prs(iommu->ecap)) in free_dmar_iommu()
1434 intel_svm_finish_prq(iommu); in free_dmar_iommu()
1478 int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) in domain_attach_iommu() argument
1491 spin_lock(&iommu->lock); in domain_attach_iommu()
1492 curr = xa_load(&domain->iommu_array, iommu->seq_id); in domain_attach_iommu()
1495 spin_unlock(&iommu->lock); in domain_attach_iommu()
1500 ndomains = cap_ndoms(iommu->cap); in domain_attach_iommu()
1501 num = find_first_zero_bit(iommu->domain_ids, ndomains); in domain_attach_iommu()
1503 pr_err("%s: No free domain ids\n", iommu->name); in domain_attach_iommu()
1507 set_bit(num, iommu->domain_ids); in domain_attach_iommu()
1510 info->iommu = iommu; in domain_attach_iommu()
1511 curr = xa_cmpxchg(&domain->iommu_array, iommu->seq_id, in domain_attach_iommu()
1519 spin_unlock(&iommu->lock); in domain_attach_iommu()
1523 clear_bit(info->did, iommu->domain_ids); in domain_attach_iommu()
1525 spin_unlock(&iommu->lock); in domain_attach_iommu()
1530 void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) in domain_detach_iommu() argument
1537 spin_lock(&iommu->lock); in domain_detach_iommu()
1538 info = xa_load(&domain->iommu_array, iommu->seq_id); in domain_detach_iommu()
1540 clear_bit(info->did, iommu->domain_ids); in domain_detach_iommu()
1541 xa_erase(&domain->iommu_array, iommu->seq_id); in domain_detach_iommu()
1546 spin_unlock(&iommu->lock); in domain_detach_iommu()
1588 static void copied_context_tear_down(struct intel_iommu *iommu, in copied_context_tear_down() argument
1594 if (!context_copied(iommu, bus, devfn)) in copied_context_tear_down()
1597 assert_spin_locked(&iommu->lock); in copied_context_tear_down()
1602 if (did_old < cap_ndoms(iommu->cap)) { in copied_context_tear_down()
1603 iommu->flush.flush_context(iommu, did_old, in copied_context_tear_down()
1607 iommu->flush.flush_iotlb(iommu, did_old, 0, 0, in copied_context_tear_down()
1611 clear_context_copied(iommu, bus, devfn); in copied_context_tear_down()
1620 static void context_present_cache_flush(struct intel_iommu *iommu, u16 did, in context_present_cache_flush() argument
1623 if (cap_caching_mode(iommu->cap)) { in context_present_cache_flush()
1624 iommu->flush.flush_context(iommu, 0, in context_present_cache_flush()
1628 iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); in context_present_cache_flush()
1630 iommu_flush_write_buffer(iommu); in context_present_cache_flush()
1635 struct intel_iommu *iommu, in domain_context_mapping_one() argument
1639 domain_lookup_dev_info(domain, iommu, bus, devfn); in domain_context_mapping_one()
1640 u16 did = domain_id_iommu(domain, iommu); in domain_context_mapping_one()
1649 spin_lock(&iommu->lock); in domain_context_mapping_one()
1651 context = iommu_context_addr(iommu, bus, devfn, 1); in domain_context_mapping_one()
1656 if (context_present(context) && !context_copied(iommu, bus, devfn)) in domain_context_mapping_one()
1659 copied_context_tear_down(iommu, context, bus, devfn); in domain_context_mapping_one()
1665 * Skip top levels of page tables for iommu which has in domain_context_mapping_one()
1668 for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { in domain_context_mapping_one()
1685 if (!ecap_coherent(iommu->ecap)) in domain_context_mapping_one()
1687 context_present_cache_flush(iommu, did, bus, devfn); in domain_context_mapping_one()
1691 spin_unlock(&iommu->lock); in domain_context_mapping_one()
1700 struct intel_iommu *iommu = info->iommu; in domain_context_mapping_cb() local
1703 return domain_context_mapping_one(domain, iommu, in domain_context_mapping_cb()
1711 struct intel_iommu *iommu = info->iommu; in domain_context_mapping() local
1715 return domain_context_mapping_one(domain, iommu, bus, devfn); in domain_context_mapping()
1890 struct intel_iommu *iommu = info->iommu; in domain_context_clear_one() local
1894 spin_lock(&iommu->lock); in domain_context_clear_one()
1895 context = iommu_context_addr(iommu, bus, devfn, 0); in domain_context_clear_one()
1897 spin_unlock(&iommu->lock); in domain_context_clear_one()
1903 __iommu_flush_cache(iommu, context, sizeof(*context)); in domain_context_clear_one()
1904 spin_unlock(&iommu->lock); in domain_context_clear_one()
1908 static int domain_setup_first_level(struct intel_iommu *iommu, in domain_setup_first_level() argument
1918 * Skip top levels of page tables for iommu which has in domain_setup_first_level()
1921 for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { in domain_setup_first_level()
1937 return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid, in domain_setup_first_level()
1938 domain_id_iommu(domain, iommu), in domain_setup_first_level()
1952 struct intel_iommu *iommu = info->iommu; in dmar_domain_attach_device() local
1956 ret = domain_attach_iommu(domain, iommu); in dmar_domain_attach_device()
1968 if (!sm_supported(iommu)) in dmar_domain_attach_device()
1971 ret = domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID); in dmar_domain_attach_device()
1973 ret = intel_pasid_setup_second_level(iommu, domain, dev, IOMMU_NO_PASID); in dmar_domain_attach_device()
2023 struct intel_iommu *iommu = info->iommu; in device_def_domain_type() local
2029 if (!ecap_pass_through(iommu->ecap)) in device_def_domain_type()
2042 static void intel_iommu_init_qi(struct intel_iommu *iommu) in intel_iommu_init_qi() argument
2045 * Start from the sane iommu hardware state. in intel_iommu_init_qi()
2050 if (!iommu->qi) { in intel_iommu_init_qi()
2054 dmar_fault(-1, iommu); in intel_iommu_init_qi()
2059 dmar_disable_qi(iommu); in intel_iommu_init_qi()
2062 if (dmar_enable_qi(iommu)) { in intel_iommu_init_qi()
2066 iommu->flush.flush_context = __iommu_flush_context; in intel_iommu_init_qi()
2067 iommu->flush.flush_iotlb = __iommu_flush_iotlb; in intel_iommu_init_qi()
2069 iommu->name); in intel_iommu_init_qi()
2071 iommu->flush.flush_context = qi_flush_context; in intel_iommu_init_qi()
2072 iommu->flush.flush_iotlb = qi_flush_iotlb; in intel_iommu_init_qi()
2073 pr_info("%s: Using Queued invalidation\n", iommu->name); in intel_iommu_init_qi()
2077 static int copy_context_table(struct intel_iommu *iommu, in copy_context_table() argument
2099 __iommu_flush_cache(iommu, new_ce, in copy_context_table()
2129 new_ce = iommu_alloc_page_node(iommu->node, GFP_KERNEL); in copy_context_table()
2143 if (did >= 0 && did < cap_ndoms(iommu->cap)) in copy_context_table()
2144 set_bit(did, iommu->domain_ids); in copy_context_table()
2146 set_context_copied(iommu, bus, devfn); in copy_context_table()
2152 __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE); in copy_context_table()
2161 static int copy_translation_tables(struct intel_iommu *iommu) in copy_translation_tables() argument
2171 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); in copy_translation_tables()
2173 new_ext = !!sm_supported(iommu); in copy_translation_tables()
2184 iommu->copied_tables = bitmap_zalloc(BIT_ULL(16), GFP_KERNEL); in copy_translation_tables()
2185 if (!iommu->copied_tables) in copy_translation_tables()
2204 ret = copy_context_table(iommu, &old_rt[bus], in copy_translation_tables()
2208 iommu->name, bus); in copy_translation_tables()
2213 spin_lock(&iommu->lock); in copy_translation_tables()
2222 iommu->root_entry[bus].lo = val; in copy_translation_tables()
2229 iommu->root_entry[bus].hi = val; in copy_translation_tables()
2232 spin_unlock(&iommu->lock); in copy_translation_tables()
2236 __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE); in copy_translation_tables()
2249 struct intel_iommu *iommu; in init_dmars() local
2256 for_each_iommu(iommu, drhd) { in init_dmars()
2258 iommu_disable_translation(iommu); in init_dmars()
2263 * Find the max pasid size of all IOMMU's in the system. in init_dmars()
2267 if (pasid_supported(iommu)) { in init_dmars()
2268 u32 temp = 2 << ecap_pss(iommu->ecap); in init_dmars()
2274 intel_iommu_init_qi(iommu); in init_dmars()
2276 ret = iommu_init_domains(iommu); in init_dmars()
2280 init_translation_status(iommu); in init_dmars()
2282 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_dmars()
2283 iommu_disable_translation(iommu); in init_dmars()
2284 clear_translation_pre_enabled(iommu); in init_dmars()
2286 iommu->name); in init_dmars()
2292 * among all IOMMU's. Need to Split it later. in init_dmars()
2294 ret = iommu_alloc_root_entry(iommu); in init_dmars()
2298 if (translation_pre_enabled(iommu)) { in init_dmars()
2301 ret = copy_translation_tables(iommu); in init_dmars()
2304 * We found the IOMMU with translation in init_dmars()
2313 iommu->name); in init_dmars()
2314 iommu_disable_translation(iommu); in init_dmars()
2315 clear_translation_pre_enabled(iommu); in init_dmars()
2318 iommu->name); in init_dmars()
2322 intel_svm_check(iommu); in init_dmars()
2330 for_each_active_iommu(iommu, drhd) { in init_dmars()
2331 iommu_flush_write_buffer(iommu); in init_dmars()
2332 iommu_set_root_entry(iommu); in init_dmars()
2344 for_each_iommu(iommu, drhd) { in init_dmars()
2351 iommu_disable_protect_mem_regions(iommu); in init_dmars()
2355 iommu_flush_write_buffer(iommu); in init_dmars()
2358 if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { in init_dmars()
2364 ret = intel_svm_enable_prq(iommu); in init_dmars()
2370 ret = dmar_set_interrupt(iommu); in init_dmars()
2378 for_each_active_iommu(iommu, drhd) { in init_dmars()
2379 disable_dmar_iommu(iommu); in init_dmars()
2380 free_dmar_iommu(iommu); in init_dmars()
2414 /* This IOMMU has *only* gfx devices. Either bypass it or in init_no_remapping_devices()
2426 struct intel_iommu *iommu = NULL; in init_iommu_hw() local
2429 for_each_active_iommu(iommu, drhd) { in init_iommu_hw()
2430 if (iommu->qi) { in init_iommu_hw()
2431 ret = dmar_reenable_qi(iommu); in init_iommu_hw()
2437 for_each_iommu(iommu, drhd) { in init_iommu_hw()
2444 iommu_disable_protect_mem_regions(iommu); in init_iommu_hw()
2448 iommu_flush_write_buffer(iommu); in init_iommu_hw()
2449 iommu_set_root_entry(iommu); in init_iommu_hw()
2450 iommu_enable_translation(iommu); in init_iommu_hw()
2451 iommu_disable_protect_mem_regions(iommu); in init_iommu_hw()
2460 struct intel_iommu *iommu; in iommu_flush_all() local
2462 for_each_active_iommu(iommu, drhd) { in iommu_flush_all()
2463 iommu->flush.flush_context(iommu, 0, 0, 0, in iommu_flush_all()
2465 iommu->flush.flush_iotlb(iommu, 0, 0, 0, in iommu_flush_all()
2473 struct intel_iommu *iommu = NULL; in iommu_suspend() local
2478 for_each_active_iommu(iommu, drhd) { in iommu_suspend()
2479 iommu_disable_translation(iommu); in iommu_suspend()
2481 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_suspend()
2483 iommu->iommu_state[SR_DMAR_FECTL_REG] = in iommu_suspend()
2484 readl(iommu->reg + DMAR_FECTL_REG); in iommu_suspend()
2485 iommu->iommu_state[SR_DMAR_FEDATA_REG] = in iommu_suspend()
2486 readl(iommu->reg + DMAR_FEDATA_REG); in iommu_suspend()
2487 iommu->iommu_state[SR_DMAR_FEADDR_REG] = in iommu_suspend()
2488 readl(iommu->reg + DMAR_FEADDR_REG); in iommu_suspend()
2489 iommu->iommu_state[SR_DMAR_FEUADDR_REG] = in iommu_suspend()
2490 readl(iommu->reg + DMAR_FEUADDR_REG); in iommu_suspend()
2492 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_suspend()
2500 struct intel_iommu *iommu = NULL; in iommu_resume() local
2505 panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); in iommu_resume()
2507 WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); in iommu_resume()
2511 for_each_active_iommu(iommu, drhd) { in iommu_resume()
2513 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_resume()
2515 writel(iommu->iommu_state[SR_DMAR_FECTL_REG], in iommu_resume()
2516 iommu->reg + DMAR_FECTL_REG); in iommu_resume()
2517 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], in iommu_resume()
2518 iommu->reg + DMAR_FEDATA_REG); in iommu_resume()
2519 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], in iommu_resume()
2520 iommu->reg + DMAR_FEADDR_REG); in iommu_resume()
2521 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], in iommu_resume()
2522 iommu->reg + DMAR_FEUADDR_REG); in iommu_resume()
2524 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_resume()
2750 struct intel_iommu *iommu = dmaru->iommu; in intel_iommu_add() local
2752 ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_DMAR, iommu); in intel_iommu_add()
2756 sp = domain_update_iommu_superpage(NULL, iommu) - 1; in intel_iommu_add()
2757 if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { in intel_iommu_add()
2759 iommu->name); in intel_iommu_add()
2766 if (iommu->gcmd & DMA_GCMD_TE) in intel_iommu_add()
2767 iommu_disable_translation(iommu); in intel_iommu_add()
2769 ret = iommu_init_domains(iommu); in intel_iommu_add()
2771 ret = iommu_alloc_root_entry(iommu); in intel_iommu_add()
2775 intel_svm_check(iommu); in intel_iommu_add()
2782 iommu_disable_protect_mem_regions(iommu); in intel_iommu_add()
2786 intel_iommu_init_qi(iommu); in intel_iommu_add()
2787 iommu_flush_write_buffer(iommu); in intel_iommu_add()
2790 if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { in intel_iommu_add()
2791 ret = intel_svm_enable_prq(iommu); in intel_iommu_add()
2796 ret = dmar_set_interrupt(iommu); in intel_iommu_add()
2800 iommu_set_root_entry(iommu); in intel_iommu_add()
2801 iommu_enable_translation(iommu); in intel_iommu_add()
2803 iommu_disable_protect_mem_regions(iommu); in intel_iommu_add()
2807 disable_dmar_iommu(iommu); in intel_iommu_add()
2809 free_dmar_iommu(iommu); in intel_iommu_add()
2816 struct intel_iommu *iommu = dmaru->iommu; in dmar_iommu_hotplug() local
2820 if (iommu == NULL) in dmar_iommu_hotplug()
2826 disable_dmar_iommu(iommu); in dmar_iommu_hotplug()
2827 free_dmar_iommu(iommu); in dmar_iommu_hotplug()
2880 static int dmar_ats_supported(struct pci_dev *dev, struct intel_iommu *iommu) in dmar_ats_supported() argument
2895 * When IOMMU is in legacy mode, enabling ATS is done in dmar_ats_supported()
2900 return !(satcu->atc_required && !sm_supported(iommu)); in dmar_ats_supported()
3008 struct intel_iommu *iommu = NULL; in intel_disable_iommus() local
3011 for_each_iommu(iommu, drhd) in intel_disable_iommus()
3012 iommu_disable_translation(iommu); in intel_disable_iommus()
3018 struct intel_iommu *iommu = NULL; in intel_iommu_shutdown() local
3026 for_each_iommu(iommu, drhd) in intel_iommu_shutdown()
3027 iommu_disable_protect_mem_regions(iommu); in intel_iommu_shutdown()
3039 return container_of(iommu_dev, struct intel_iommu, iommu); in dev_to_intel_iommu()
3045 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in version_show() local
3046 u32 ver = readl(iommu->reg + DMAR_VER_REG); in version_show()
3055 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in address_show() local
3056 return sysfs_emit(buf, "%llx\n", iommu->reg_phys); in address_show()
3063 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in cap_show() local
3064 return sysfs_emit(buf, "%llx\n", iommu->cap); in cap_show()
3071 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in ecap_show() local
3072 return sysfs_emit(buf, "%llx\n", iommu->ecap); in ecap_show()
3079 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in domains_supported_show() local
3080 return sysfs_emit(buf, "%ld\n", cap_ndoms(iommu->cap)); in domains_supported_show()
3087 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in domains_used_show() local
3089 bitmap_weight(iommu->domain_ids, in domains_used_show()
3090 cap_ndoms(iommu->cap))); in domains_used_show()
3105 .name = "intel-iommu",
3133 pr_info("Intel-IOMMU force enabled due to platform opt in\n"); in platform_optin_force_iommu()
3136 * If Intel-IOMMU is disabled by default, we will apply identity in platform_optin_force_iommu()
3152 struct intel_iommu *iommu __maybe_unused; in probe_acpi_namespace_devices()
3156 for_each_active_iommu(iommu, drhd) { in probe_acpi_namespace_devices()
3189 pr_warn("Forcing Intel-IOMMU to enabled\n"); in tboot_force_iommu()
3201 struct intel_iommu *iommu; in intel_iommu_init() local
3204 * Intel IOMMU is required for a TXT/tboot launch or platform in intel_iommu_init()
3238 * We exit the function here to ensure IOMMU's remapping and in intel_iommu_init()
3239 * mempool aren't setup, which means that the IOMMU's PMRs in intel_iommu_init()
3246 for_each_iommu(iommu, drhd) in intel_iommu_init()
3247 iommu_disable_protect_mem_regions(iommu); in intel_iommu_init()
3282 for_each_active_iommu(iommu, drhd) { in intel_iommu_init()
3288 * the virtual and physical IOMMU page-tables. in intel_iommu_init()
3290 if (cap_caching_mode(iommu->cap) && in intel_iommu_init()
3292 pr_info_once("IOMMU batching disallowed due to virtualization\n"); in intel_iommu_init()
3295 iommu_device_sysfs_add(&iommu->iommu, NULL, in intel_iommu_init()
3297 "%s", iommu->name); in intel_iommu_init()
3298 iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); in intel_iommu_init()
3300 iommu_pmu_register(iommu); in intel_iommu_init()
3307 for_each_iommu(iommu, drhd) { in intel_iommu_init()
3308 if (!drhd->ignored && !translation_pre_enabled(iommu)) in intel_iommu_init()
3309 iommu_enable_translation(iommu); in intel_iommu_init()
3311 iommu_disable_protect_mem_regions(iommu); in intel_iommu_init()
3336 * NB - intel-iommu lacks any sort of reference counting for the users of
3360 struct intel_iommu *iommu = info->iommu; in device_block_translation() local
3365 if (sm_supported(iommu)) in device_block_translation()
3366 intel_pasid_tear_down_entry(iommu, dev, in device_block_translation()
3380 domain_detach_iommu(info->domain, iommu); in device_block_translation()
3419 static int iommu_superpage_capability(struct intel_iommu *iommu, bool first_stage) in iommu_superpage_capability() argument
3425 return cap_fl1gp_support(iommu->cap) ? 2 : 1; in iommu_superpage_capability()
3427 return fls(cap_super_page_val(iommu->cap)); in iommu_superpage_capability()
3433 struct intel_iommu *iommu = info->iommu; in paging_domain_alloc() local
3452 addr_width = agaw_to_width(iommu->agaw); in paging_domain_alloc()
3453 if (addr_width > cap_mgaw(iommu->cap)) in paging_domain_alloc()
3454 addr_width = cap_mgaw(iommu->cap); in paging_domain_alloc()
3456 domain->agaw = iommu->agaw; in paging_domain_alloc()
3459 /* iommu memory access coherency */ in paging_domain_alloc()
3460 domain->iommu_coherency = iommu_paging_structure_coherency(iommu); in paging_domain_alloc()
3464 domain->iommu_superpage = iommu_superpage_capability(iommu, first_stage); in paging_domain_alloc()
3532 struct intel_iommu *iommu = info->iommu; in intel_iommu_domain_alloc_user() local
3538 if (!nested_supported(iommu) || flags) in intel_iommu_domain_alloc_user()
3546 if (nested_parent && !nested_supported(iommu)) in intel_iommu_domain_alloc_user()
3548 if (user_data || (dirty_tracking && !ssads_supported(iommu))) in intel_iommu_domain_alloc_user()
3591 struct intel_iommu *iommu = info->iommu; in prepare_domain_attach_device() local
3594 if (dmar_domain->force_snooping && !ecap_sc_support(iommu->ecap)) in prepare_domain_attach_device()
3597 if (domain->dirty_ops && !ssads_supported(iommu)) in prepare_domain_attach_device()
3600 /* check if this iommu agaw is sufficient for max mapped address */ in prepare_domain_attach_device()
3601 addr_width = agaw_to_width(iommu->agaw); in prepare_domain_attach_device()
3602 if (addr_width > cap_mgaw(iommu->cap)) in prepare_domain_attach_device()
3603 addr_width = cap_mgaw(iommu->cap); in prepare_domain_attach_device()
3612 while (iommu->agaw < dmar_domain->agaw) { in prepare_domain_attach_device()
3623 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev) && in prepare_domain_attach_device()
3624 context_copied(iommu, info->bus, info->devfn)) in prepare_domain_attach_device()
3666 pr_err("%s: iommu width (%d) is not " in intel_iommu_map()
3781 if (!ecap_sc_support(info->iommu->ecap)) { in domain_support_force_snooping()
3805 intel_pasid_setup_page_snoop_control(info->iommu, info->dev, in domain_set_force_snooping()
3842 return ecap_sc_support(info->iommu->ecap); in intel_iommu_capable()
3844 return ssads_supported(info->iommu); in intel_iommu_capable()
3854 struct intel_iommu *iommu; in intel_iommu_probe_device() local
3858 iommu = device_lookup_iommu(dev, &bus, &devfn); in intel_iommu_probe_device()
3859 if (!iommu || !iommu->iommu.ops) in intel_iommu_probe_device()
3873 info->segment = iommu->segment; in intel_iommu_probe_device()
3877 info->iommu = iommu; in intel_iommu_probe_device()
3879 if (ecap_dev_iotlb_support(iommu->ecap) && in intel_iommu_probe_device()
3881 dmar_ats_supported(pdev, iommu)) { in intel_iommu_probe_device()
3886 * For IOMMU that supports device IOTLB throttling in intel_iommu_probe_device()
3888 * of a VF such that IOMMU HW can gauge queue depth in intel_iommu_probe_device()
3892 if (ecap_dit(iommu->ecap)) in intel_iommu_probe_device()
3896 if (sm_supported(iommu)) { in intel_iommu_probe_device()
3897 if (pasid_supported(iommu)) { in intel_iommu_probe_device()
3904 if (info->ats_supported && ecap_prs(iommu->ecap) && in intel_iommu_probe_device()
3913 ret = device_rbtree_insert(iommu, info); in intel_iommu_probe_device()
3918 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) { in intel_iommu_probe_device()
3925 if (!context_copied(iommu, info->bus, info->devfn)) { in intel_iommu_probe_device()
3944 return &iommu->iommu; in intel_iommu_probe_device()
3958 struct intel_iommu *iommu = info->iommu; in intel_iommu_release_device() local
3965 mutex_lock(&iommu->iopf_lock); in intel_iommu_release_device()
3968 mutex_unlock(&iommu->iopf_lock); in intel_iommu_release_device()
3970 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev) && in intel_iommu_release_device()
3971 !context_copied(iommu, info->bus, info->devfn)) in intel_iommu_release_device()
4049 struct intel_iommu *iommu; in intel_iommu_enable_sva() local
4054 iommu = info->iommu; in intel_iommu_enable_sva()
4055 if (!iommu) in intel_iommu_enable_sva()
4058 if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE)) in intel_iommu_enable_sva()
4066 * support PCI/PRI. The IOMMU side has no means to check the in intel_iommu_enable_sva()
4067 * capability of device-specific IOPF. Therefore, IOMMU can only in intel_iommu_enable_sva()
4083 struct intel_iommu *iommu = info->iommu; in context_flip_pri() local
4088 spin_lock(&iommu->lock); in context_flip_pri()
4089 if (context_copied(iommu, bus, devfn)) { in context_flip_pri()
4090 spin_unlock(&iommu->lock); in context_flip_pri()
4094 context = iommu_context_addr(iommu, bus, devfn, false); in context_flip_pri()
4096 spin_unlock(&iommu->lock); in context_flip_pri()
4106 if (!ecap_coherent(iommu->ecap)) in context_flip_pri()
4109 spin_unlock(&iommu->lock); in context_flip_pri()
4118 struct intel_iommu *iommu; in intel_iommu_enable_iopf() local
4127 iommu = info->iommu; in intel_iommu_enable_iopf()
4128 if (!iommu) in intel_iommu_enable_iopf()
4139 ret = iopf_queue_add_device(iommu->iopf_queue, dev); in intel_iommu_enable_iopf()
4157 iopf_queue_remove_device(iommu->iopf_queue, dev); in intel_iommu_enable_iopf()
4165 struct intel_iommu *iommu = info->iommu; in intel_iommu_disable_iopf() local
4177 iopf_queue_remove_device(iommu->iopf_queue, dev); in intel_iommu_disable_iopf()
4227 return translation_pre_enabled(info->iommu) && !info->domain; in intel_iommu_is_attach_deferred()
4233 * thus not be able to bypass the IOMMU restrictions.
4239 "Skipping IOMMU quirk for dev [%04X:%04X] on untrusted PCI link\n", in risky_device()
4260 struct intel_iommu *iommu = info->iommu; in intel_iommu_remove_dev_pasid() local
4265 intel_pasid_tear_down_entry(iommu, dev, pasid, false); in intel_iommu_remove_dev_pasid()
4282 domain_detach_iommu(dmar_domain, iommu); in intel_iommu_remove_dev_pasid()
4285 intel_pasid_tear_down_entry(iommu, dev, pasid, false); in intel_iommu_remove_dev_pasid()
4294 struct intel_iommu *iommu = info->iommu; in intel_iommu_set_dev_pasid() local
4299 if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) in intel_iommu_set_dev_pasid()
4305 if (context_copied(iommu, info->bus, info->devfn)) in intel_iommu_set_dev_pasid()
4316 ret = domain_attach_iommu(dmar_domain, iommu); in intel_iommu_set_dev_pasid()
4325 ret = domain_setup_first_level(iommu, dmar_domain, in intel_iommu_set_dev_pasid()
4328 ret = intel_pasid_setup_second_level(iommu, dmar_domain, in intel_iommu_set_dev_pasid()
4346 domain_detach_iommu(dmar_domain, iommu); in intel_iommu_set_dev_pasid()
4355 struct intel_iommu *iommu = info->iommu; in intel_iommu_hw_info() local
4363 vtd->cap_reg = iommu->cap; in intel_iommu_hw_info()
4364 vtd->ecap_reg = iommu->ecap; in intel_iommu_hw_info()
4380 ret = intel_pasid_setup_dirty_tracking(info->iommu, info->dev, in device_set_dirty_tracking()
4497 struct intel_iommu *iommu = info->iommu; in context_setup_pass_through() local
4500 spin_lock(&iommu->lock); in context_setup_pass_through()
4501 context = iommu_context_addr(iommu, bus, devfn, 1); in context_setup_pass_through()
4503 spin_unlock(&iommu->lock); in context_setup_pass_through()
4507 if (context_present(context) && !context_copied(iommu, bus, devfn)) { in context_setup_pass_through()
4508 spin_unlock(&iommu->lock); in context_setup_pass_through()
4512 copied_context_tear_down(iommu, context, bus, devfn); in context_setup_pass_through()
4520 context_set_address_width(context, iommu->msagaw); in context_setup_pass_through()
4524 if (!ecap_coherent(iommu->ecap)) in context_setup_pass_through()
4526 context_present_cache_flush(iommu, FLPT_DEFAULT_DID, bus, devfn); in context_setup_pass_through()
4527 spin_unlock(&iommu->lock); in context_setup_pass_through()
4556 struct intel_iommu *iommu = info->iommu; in identity_domain_attach_dev() local
4564 if (sm_supported(iommu)) { in identity_domain_attach_dev()
4565 ret = intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); in identity_domain_attach_dev()
4579 struct intel_iommu *iommu = info->iommu; in identity_domain_set_dev_pasid() local
4581 if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) in identity_domain_set_dev_pasid()
4584 return intel_pasid_setup_pass_through(iommu, dev, pasid); in identity_domain_set_dev_pasid()
4636 pci_info(dev, "Disabling IOMMU for graphics on this chipset\n"); in quirk_iommu_igfx()
4717 pci_info(dev, "BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); in quirk_calpella_no_shadow_gtt()
4746 pci_info(dev, "Skip IOMMU disabling for graphics\n"); in quirk_igfx_skip_te_disable()
4840 * before unmap/unbind. For #3, iommu driver gets mmu_notifier to
4857 qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, in quirk_extra_dev_tlb_flush()
4860 qi_flush_dev_iotlb_pasid(info->iommu, sid, info->pfsid, in quirk_extra_dev_tlb_flush()
4879 int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob) in ecmd_submit_sync() argument
4885 if (!cap_ecmds(iommu->cap)) in ecmd_submit_sync()
4888 raw_spin_lock_irqsave(&iommu->register_lock, flags); in ecmd_submit_sync()
4890 res = dmar_readq(iommu->reg + DMAR_ECRSP_REG); in ecmd_submit_sync()
4903 dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); in ecmd_submit_sync()
4904 dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); in ecmd_submit_sync()
4906 IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq, in ecmd_submit_sync()
4916 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in ecmd_submit_sync()