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/linux/drivers/iommu/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
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H A Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
58 struct iommu_device iommu; member
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H A Domap-iommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * omap iommu: main structures
5 * Copyright (C) 2008-2009 Nokia Corporation
14 #include <linux/iommu.h>
29 * struct omap_iommu_device - omap iommu device data
30 * @pgtable: page table used by an omap iommu attached to a domain
31 * @iommu_dev: pointer to store an omap iommu instance attached to a domain
39 * struct omap_iommu_domain - omap iommu domain
41 * @iommus: omap iommu device data for all iommus in this domain
44 * @domain: generic domain handle used by iommu core code
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H A Domap-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap iommu: tlb and pagetable primitives
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
19 #include <linux/omap-iommu.h>
30 #include <linux/platform_data/iommu-omap.h>
32 #include "omap-iopgtable.h"
33 #include "omap-iommu.h"
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/linux/arch/sparc/kernel/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* iommu.c: Generic sparc64 IOMMU support.
13 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
28 #define STC_CTXMATCH_ADDR(STC, CTX) \ argument
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
31 (*((STC)->strbuf_flushflag) = 0UL)
33 (*((STC)->strbuf_flushflag) != 0UL)
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H A Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
49 /* IOMMU control register. */
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
61 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
62 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
61 /* Helper function of IOMMU error checking, which checks out
62 * the state of the streaming buffers. The IOMMU lock is
90 * interrogate the IOMMU state to see if it is the cause.
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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/linux/drivers/iommu/arm/arm-smmu/
H A Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
62 u8 asid; /* asid and ctx bank # are 1:1 */
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/linux/drivers/gpu/host1x/
H A Dcontext.c1 // SPDX-License-Identifier: GPL-2.0-only
23 struct host1x_memory_context_list *cdl = &host1x->context_list; in host1x_memory_context_list_init()
24 struct device_node *node = host1x->dev->of_node; in host1x_memory_context_list_init()
25 struct host1x_memory_context *ctx; in host1x_memory_context_list_init() local
29 cdl->devs = NULL; in host1x_memory_context_list_init()
30 cdl->len = 0; in host1x_memory_context_list_init()
31 mutex_init(&cdl->lock); in host1x_memory_context_list_init()
33 err = of_property_count_u32_elems(node, "iommu-map"); in host1x_memory_context_list_init()
37 cdl->len = err / 4; in host1x_memory_context_list_init()
38 cdl->devs = kcalloc(cdl->len, sizeof(*cdl->devs), GFP_KERNEL); in host1x_memory_context_list_init()
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
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H A Dmsm8953.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
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/linux/drivers/accel/ivpu/
H A Divpu_gem.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
6 #include <linux/dma-buf.h>
28 …"%6s: bo %8p vpu_addr %9llx size %8zu ctx %d has_pages %d dma_mapped %d mmu_mapped %d wc %d import… in ivpu_dbg_bo()
29 action, bo, bo->vpu_addr, ivpu_bo_size(bo), bo->ctx ? bo->ctx->id : 0, in ivpu_dbg_bo()
30 (bool)bo->base.pages, (bool)bo->base.sgt, bo->mmu_mapped, bo->base.map_wc, in ivpu_dbg_bo()
31 (bool)bo->base.base.import_attach); in ivpu_dbg_bo()
35 * ivpu_bo_pin() - pin the backing physical pages and map them to VPU.
38 * to IOMMU address space and finally updates the VPU MMU page tables
39 * to allow the VPU to translate VPU address to IOMMU address.
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/linux/drivers/gpu/drm/msm/
H A Dmsm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
28 * - 1.0.0 - initial interface
29 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
30 * - 1.2.0 - adds explicit fence support for submit ioctl
31 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
34 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
36 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
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H A Dmsm_gem.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-map-ops.h>
11 #include <linux/dma-buf.h>
28 struct msm_drm_private *priv = obj->dev->dev_private; in physaddr()
29 return (((dma_addr_t)msm_obj->vram_node->start) << PAGE_SHIFT) + in physaddr()
30 priv->vram.paddr; in physaddr()
36 return !msm_obj->vram_node; in use_pages()
41 uint64_t total_mem = atomic64_add_return(size, &priv->total_mem); in update_device_mem()
47 struct msm_file_private *ctx = file->driver_priv; in update_ctx_mem() local
48 uint64_t ctx_mem = atomic64_add_return(size, &ctx->ctx_mem); in update_ctx_mem()
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/linux/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "regs-decon7.h"
82 .compatible = "samsung,exynos7-decon",
86 .compatible = "samsung,exynos7870-decon",
111 * decon_shadow_protect_win() - disable updating values from shadow registers at vsync
113 * @ctx: display and enhancement controller context
117 static void decon_shadow_protect_win(struct decon_context *ctx, in decon_shadow_protect_win() argument
121 unsigned int shift = ctx->data->shadowcon_win_protect_shift; in decon_shadow_protect_win()
125 val = readl(ctx->regs + SHADOWCON); in decon_shadow_protect_win()
130 writel(val, ctx->regs + SHADOWCON); in decon_shadow_protect_win()
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H A Dexynos5433_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "regs-decon5433.h"
96 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, in decon_set_bits() argument
99 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); in decon_set_bits()
100 writel(val, ctx->addr + reg); in decon_set_bits()
105 struct decon_context *ctx = crtc->ctx; in decon_enable_vblank() local
109 if (crtc->i80_mode) in decon_enable_vblank()
114 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank()
116 enable_irq(ctx->irq); in decon_enable_vblank()
117 if (!(ctx->out_type & I80_HW_TRG)) in decon_enable_vblank()
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/linux/drivers/crypto/caam/
H A Dcaamalg_qi2.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
12 #include <soc/fsl/dpaa2-io.h>
13 #include <soc/fsl/dpaa2-fd.h>
30 * dpaa2_caam_priv - driver private data
43 * @domain: IOMMU domain
71 * dpaa2_caam_priv_per_cpu - per CPU private data
76 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
98 * aead_edesc - s/w-extended aead descriptor
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/linux/drivers/vhost/
H A Dvdpa.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2020 Intel Corporation.
20 #include <linux/iommu.h>
77 return as->id; in iotlb_to_asid()
82 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in asid_to_as()
86 if (as->id == asid) in asid_to_as()
99 return &as->iotlb; in asid_to_iotlb()
104 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in vhost_vdpa_alloc_as()
110 if (asid >= v->vdpa->nas) in vhost_vdpa_alloc_as()
117 vhost_iotlb_init(&as->iotlb, 0, 0); in vhost_vdpa_alloc_as()
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/linux/drivers/virtio/
H A Dvirtio_ring.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/dma-mapping.h>
22 dev_err(&(_vq)->vq.vdev->dev, \
23 "%s:"fmt, (_vq)->vq.name, ##args); \
29 if ((_vq)->in_use) \
31 (_vq)->vq.name, (_vq)->in_use); \
32 (_vq)->in_use = __LINE__; \
35 do { BUG_ON(!(_vq)->in_use); (_vq)->in_use = 0; } while(0)
41 if ((_vq)->last_add_time_valid) \
43 (_vq)->last_add_time)) > 100); \
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ttm.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
41 #include <linux/dma-buf.h>
78 return ttm_range_man_init(&adev->mman.bdev, type, in amdgpu_ttm_init_on_chip()
83 * amdgpu_evict_flags - Compute placement flags
93 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); in amdgpu_evict_flags()
103 if (bo->type == ttm_bo_type_sg) { in amdgpu_evict_flags()
104 placement->num_placement = 0; in amdgpu_evict_flags()
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/linux/drivers/gpu/drm/i915/
H A Di915_gpu_error.c69 sg->page_link = (unsigned long)virt_to_page(addr); in __sg_set_buf()
70 sg->offset = offset_in_page(addr); in __sg_set_buf()
71 sg->length = len; in __sg_set_buf()
72 sg->dma_address = it; in __sg_set_buf()
80 if (e->bytes + len + 1 <= e->size) in __i915_error_grow()
83 if (e->bytes) { in __i915_error_grow()
84 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); in __i915_error_grow()
85 e->iter += e->bytes; in __i915_error_grow()
86 e->buf = NULL; in __i915_error_grow()
87 e->bytes = 0; in __i915_error_grow()
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/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
27 struct msm_ringbuffer *ring = submit->ring; in a4xx_submit()
30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
31 switch (submit->cmd[i].type) { in a4xx_submit()
33 /* ignore IB-targets */ in a4xx_submit()
36 /* ignore if there has not been a ctx switch: */ in a4xx_submit()
37 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) in a4xx_submit()
42 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a4xx_submit()
43 OUT_RING(ring, submit->cmd[i].size); in a4xx_submit()
50 OUT_RING(ring, submit->seqno); in a4xx_submit()
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/linux/drivers/dma/idxd/
H A Didxd.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/percpu-rwsem.h>
15 #include <linux/iommu.h>
29 IDXD_DEV_NONE = -1,
49 IDXD_TYPE_UNKNOWN = -1,
77 void *ctx, u32 *status);
86 #define INVALID_INT_HANDLE -1
260 IDXD_DEV_HALTED = -
434 user_ctx_dev(ctx) global() argument
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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
55 #include <linux/dma-mapping.h>
282 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
286 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
288 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
354 ARRAY_SIZE(buf) - offset, in vmw_print_bitmap()
377 drm_info(&dev_priv->drm, "Available shader model: %s.\n", in vmw_print_sm_type()
378 names[dev_priv->sm_type]); in vmw_print_sm_type()
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/linux/drivers/accel/habanalabs/common/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
14 #include <linux/iommu.h>
28 return -EBUSY; in hl_debugfs_i2c_read()
31 dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n", in hl_debugfs_i2c_read()
33 return -EINVAL; in hl_debugfs_i2c_read()
45 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, val); in hl_debugfs_i2c_read()
46 if (rc && rc != -EAGAIN) in hl_debugfs_i2c_read()
47 dev_err(hdev->dev, "Failed to read from I2C, error %d\n", rc); in hl_debugfs_i2c_read()
59 return -EBUSY; in hl_debugfs_i2c_write()
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