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/linux/drivers/iommu/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
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H A Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
58 struct iommu_device iommu; member
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H A Domap-iommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * omap iommu: main structures
5 * Copyright (C) 2008-2009 Nokia Corporation
14 #include <linux/iommu.h>
29 * struct omap_iommu_device - omap iommu device data
30 * @pgtable: page table used by an omap iommu attached to a domain
31 * @iommu_dev: pointer to store an omap iommu instance attached to a domain
39 * struct omap_iommu_domain - omap iommu domain
41 * @iommus: omap iommu device data for all iommus in this domain
44 * @domain: generic domain handle used by iommu core code
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/linux/arch/sparc/kernel/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* iommu.c: Generic sparc64 IOMMU support.
13 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
28 #define STC_CTXMATCH_ADDR(STC, CTX) \ argument
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
31 (*((STC)->strbuf_flushflag) = 0UL)
33 (*((STC)->strbuf_flushflag) != 0UL)
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H A Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
49 /* IOMMU control register. */
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
61 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
62 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
61 /* Helper function of IOMMU error checking, which checks out
62 * the state of the streaming buffers. The IOMMU lock is
90 * interrogate the IOMMU state to see if it is the cause.
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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/linux/drivers/iommu/arm/arm-smmu/
H A Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
62 u8 asid; /* asid and ctx bank # are 1:1 */
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/linux/drivers/gpu/host1x/
H A Dcontext.c1 // SPDX-License-Identifier: GPL-2.0-only
23 struct host1x_memory_context_list *cdl = &host1x->context_list; in host1x_memory_context_list_init()
24 struct device_node *node = host1x->dev->of_node; in host1x_memory_context_list_init()
25 struct host1x_memory_context *ctx; in host1x_memory_context_list_init() local
29 cdl->devs = NULL; in host1x_memory_context_list_init()
30 cdl->len = 0; in host1x_memory_context_list_init()
31 mutex_init(&cdl->lock); in host1x_memory_context_list_init()
33 err = of_property_count_u32_elems(node, "iommu-map"); in host1x_memory_context_list_init()
37 cdl->len = err / 4; in host1x_memory_context_list_init()
38 cdl->devs = kcalloc(cdl->len, sizeof(*cdl->devs), GFP_KERNEL); in host1x_memory_context_list_init()
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/linux/Documentation/devicetree/bindings/iommu/
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
18 interrupt-parent = <&intc>;
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H A Dmsm8917.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/thermal/thermal.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
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/linux/drivers/dma/idxd/
H A Dcdev.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/io-64-nonatomic-lo-hi.h>
13 #include <linux/iommu.h>
55 static void idxd_xa_pasid_remove(struct idxd_user_context *ctx);
66 struct idxd_user_context *ctx = dev_to_uctx(dev); in cr_faults_show() local
68 return sysfs_emit(buf, "%llu\n", ctx->counters[COUNTER_FAULTS]); in cr_faults_show()
75 struct idxd_user_context *ctx = dev_to_uctx(dev); in cr_fault_failures_show() local
77 return sysfs_emit(buf, "%llu\n", ctx->counters[COUNTER_FAULT_FAILS]); in cr_fault_failures_show()
83 struct idxd_user_context *ctx = dev_to_uctx(dev); in pid_show() local
85 return sysfs_emit(buf, "%u\n", ctx->pid); in pid_show()
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H A Didxd.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/percpu-rwsem.h>
15 #include <linux/iommu.h>
28 IDXD_DEV_NONE = -1,
48 IDXD_TYPE_UNKNOWN = -1,
76 void *ctx, u32 *status);
85 #define INVALID_INT_HANDLE -1
258 IDXD_DEV_HALTED = -1,
354 int nr_rdbufs; /* non-reserved read buffers */
390 return idxd->hw.gen_cap.evl_support ? in evl_ent_size()
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/linux/drivers/accel/ivpu/
H A Divpu_gem.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
6 #include <linux/dma-buf.h>
30 …"%6s: bo %8p vpu_addr %9llx size %8zu ctx %d has_pages %d dma_mapped %d mmu_mapped %d wc %d import… in ivpu_dbg_bo()
31 action, bo, bo->vpu_addr, ivpu_bo_size(bo), bo->ctx_id, in ivpu_dbg_bo()
32 (bool)bo->base.pages, (bool)bo->base.sgt, bo->mmu_mapped, bo->base.map_wc, in ivpu_dbg_bo()
33 (bool)drm_gem_is_imported(&bo->base.base)); in ivpu_dbg_bo()
38 return dma_resv_lock(bo->base.base.resv, NULL); in ivpu_bo_lock()
43 dma_resv_unlock(bo->base.base.resv); in ivpu_bo_unlock()
47 * ivpu_bo_pin() - pin the backing physical pages and map them to VPU.
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/linux/drivers/gpu/drm/msm/
H A Dmsm_gem.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-map-ops.h>
11 #include <linux/dma-buf.h>
25 uint64_t total_mem = atomic64_add_return(size, &priv->total_mem); in update_device_mem()
31 struct msm_context *ctx = file->driver_priv; in update_ctx_mem() local
32 uint64_t ctx_mem = atomic64_add_return(size, &ctx->ctx_mem); in update_ctx_mem()
34 rcu_read_lock(); /* Locks file->pid! */ in update_ctx_mem()
35 trace_gpu_mem_total(0, pid_nr(rcu_dereference(file->pid)), ctx_mem); in update_ctx_mem()
43 update_ctx_mem(file, obj->size); in msm_gem_open()
52 struct msm_context *ctx = file->driver_priv; in msm_gem_close() local
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H A Dmsm_gpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/adreno-smmu-priv.h>
49 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
51 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
98 /* Additional state for iommu faults: */
116 * struct msm_gpu_devfreq - devfreq related state
159 * Used to delay clamping to idle freq on active->idle transition.
210 * TODO move to per-ring locking where feasible (ie. submit/retire
263 /* work for handling active-list retiring: */
284 * switch-over happened early enough in mesa a6xx bringup that we
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/linux/drivers/gpu/drm/exynos/
H A Dexynos5433_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "regs-decon5433.h"
96 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, in decon_set_bits() argument
99 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); in decon_set_bits()
100 writel(val, ctx->addr + reg); in decon_set_bits()
105 struct decon_context *ctx = crtc->ctx; in decon_enable_vblank() local
109 if (crtc->i80_mode) in decon_enable_vblank()
114 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank()
116 enable_irq(ctx->irq); in decon_enable_vblank()
117 if (!(ctx->out_type & I80_HW_TRG)) in decon_enable_vblank()
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/linux/drivers/crypto/caam/
H A Dcaamalg_qi2.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
12 #include <soc/fsl/dpaa2-io.h>
13 #include <soc/fsl/dpaa2-fd.h>
30 * dpaa2_caam_priv - driver private data
43 * @domain: IOMMU domain
71 * dpaa2_caam_priv_per_cpu - per CPU private data
76 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
98 * aead_edesc - s/w-extended aead descriptor
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/linux/drivers/infiniband/hw/usnic/
H A Dusnic_ib_main.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
79 return scnprintf(buf, buf_sz, "PF: %s ", dev_name(&vf->pf->ib_dev.dev)); in usnic_ib_dump_vf_hdr()
85 usnic_vnic_dump(vf->vnic, buf, buf_sz, vf, in usnic_ib_dump_vf()
106 struct usnic_ib_ucontext *ctx; in usnic_ib_qp_grp_modify_active_to_err() local
111 BUG_ON(!mutex_is_locked(&us_ibdev->usdev_lock)); in usnic_ib_qp_grp_modify_active_to_err()
113 list_for_each_entry(ctx, &us_ibdev->ctx_list, link) { in usnic_ib_qp_grp_modify_active_to_err()
114 list_for_each_entry(qp_grp, &ctx->qp_grp_list, link) { in usnic_ib_qp_grp_modify_active_to_err()
115 cur_state = qp_grp->state; in usnic_ib_qp_grp_modify_active_to_err()
124 qp_grp->grp_id, in usnic_ib_qp_grp_modify_active_to_err()
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/linux/drivers/gpu/drm/
H A Ddrm_gpusvm.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
9 #include <linux/dma-mapping.h>
28 * for GPU-accelerated applications by allowing memory sharing and
33 * - Notifiers:
36 * recommendation of 512M or larger. They maintain a Red-BlacK tree and a
38 * tracked within a GPU SVM Red-BlacK tree and list and are dynamically
41 * - Ranges:
48 * event. As mentioned above, ranges are tracked in a notifier's Red-Black
51 * - Operations:
52 * Define the interface for driver-specific GPU SVM operations such as
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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright (c) 2009-2025 Broadcom. All Rights Reserved. The term
35 #include <linux/dma-mapping.h>
262 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
266 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
268 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
334 ARRAY_SIZE(buf) - offset, in vmw_print_bitmap()
357 drm_info(&dev_priv->drm, "Available shader model: %s.\n", in vmw_print_sm_type()
358 names[dev_priv->sm_type]); in vmw_print_sm_type()
362 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
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/linux/drivers/usb/host/
H A Dxhci-mem.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/dma-mapping.h>
19 #include "xhci-trace.h"
20 #include "xhci-debugfs.h"
36 struct device *dev = xhci_to_hcd(xhci)->self.sysdev; in xhci_segment_alloc()
42 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); in xhci_segment_alloc()
43 if (!seg->trbs) { in xhci_segment_alloc()
49 seg->bounce_buf = kzalloc_node(max_packet, flags, in xhci_segment_alloc()
51 if (!seg->bounce_buf) { in xhci_segment_alloc()
52 dma_pool_free(xhci->segment_pool, seg->trbs, dma); in xhci_segment_alloc()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gpuvm.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
23 #include <linux/dma-buf.h>
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
82 list_for_each_entry(entry, &mem->attachments, list) in kfd_mem_is_attached()
83 if (entry->bo_va->base.vm == avm) in kfd_mem_is_attached()
90 * reuse_dmamap() - Check whether adev can share the original
94 * in the same iommu group, they can share the original BO.
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) || in reuse_dmamap()
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group); in reuse_dmamap()
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/linux/arch/sparc/mm/
H A Dsrmmu.c1 // SPDX-License-Identifier: GPL-2.0
29 #include <asm/io-unit.h>
75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
109 /* XXX should we hyper_flush_whole_icache here - Anton */
158 if (size & (minsz - 1)) { in __srmmu_get_nocache()
161 size += minsz - 1; in __srmmu_get_nocache()
168 if (offset == -1) { in __srmmu_get_nocache()
215 if (vaddr & (size - 1)) { in srmmu_free_nocache()
220 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT; in srmmu_free_nocache()
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/linux/drivers/net/ethernet/sfc/
H A Drx_common.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/iommu.h>
29 * This must be at least 1 to prevent overflow, plus one packet-worth
37 struct efx_nic *efx = rx_queue->efx; in efx_reuse_page()
42 if (unlikely(!rx_queue->page_ring)) in efx_reuse_page()
44 index = rx_queue->page_remove & rx_queue->page_ptr_mask; in efx_reuse_page()
45 page = rx_queue->page_ring[index]; in efx_reuse_page()
49 rx_queue->page_ring[index] = NULL; in efx_reuse_page()
51 if (rx_queue->page_remove != rx_queue->page_add) in efx_reuse_page()
52 ++rx_queue->page_remove; in efx_reuse_page()
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