Lines Matching +full:iommu +full:- +full:ctx
1 // SPDX-License-Identifier: GPL-2.0-only
27 struct msm_ringbuffer *ring = submit->ring;
30 for (i = 0; i < submit->nr_cmds; i++) {
31 switch (submit->cmd[i].type) {
33 /* ignore IB-targets */
36 /* ignore if there has not been a ctx switch: */
37 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno)
42 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
43 OUT_RING(ring, submit->cmd[i].size);
50 OUT_RING(ring, submit->seqno);
67 OUT_RING(ring, submit->seqno);
73 * a4xx_enable_hwcg() - Program the clock control registers
158 struct msm_ringbuffer *ring = gpu->rb[0];
233 * Turn on hang detection - this spews a lot of useful information
240 (unsigned int)(a4xx_gpu->ocmem.base >> 14));
254 gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base));
255 gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base));
325 gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
328 ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);
329 len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;
336 ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data);
337 len = adreno_gpu->fw[ADRENO_FW_PFP]->size / 4;
347 return a4xx_me_init(gpu) ? 0 : -EINVAL;
376 DBG("%s", gpu->name);
380 adreno_gpu_ocmem_cleanup(&a4xx_gpu->ocmem);
388 if (!adreno_idle(gpu, gpu->rb[0]))
394 DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);
407 DBG("%s: Int status %08x", gpu->name, status);
451 /* GRAS CTX 0 */
453 /* PC CTX 0 */
455 /* VFD CTX 0 */
457 /* GRAS CTX 1 */
459 /* PC CTX 1 */
461 /* VFD CTX 1 */
527 /* GRAS CTX 0 */
529 /* PC CTX 0 */
531 /* VFD CTX 0 */
533 /* GRAS CTX 1 */
535 /* PC CTX 1 */
537 /* VFD CTX 1 */
556 return ERR_PTR(-ENOMEM);
560 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS);
619 *out_sample_rate = clk_get_rate(gpu->core_clk);
626 ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR);
627 return ring->memptrs->rptr;
659 struct msm_drm_private *priv = dev->dev_private;
660 struct platform_device *pdev = priv->gpu_pdev;
666 DRM_DEV_ERROR(dev->dev, "no a4xx device\n");
667 ret = -ENXIO;
673 ret = -ENOMEM;
677 adreno_gpu = &a4xx_gpu->base;
678 gpu = &adreno_gpu->base;
680 gpu->perfcntrs = NULL;
681 gpu->num_perfcntrs = 0;
687 adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :
691 ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,
692 &a4xx_gpu->ocmem);
696 adreno_gpu->uche_trap_base = 0xffff0000ffff0000ull;
698 icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");
704 ocmem_icc_path = devm_of_icc_get(&pdev->dev, "ocmem");
707 /* allow -ENODATA, ocmem icc is optional */
708 if (ret != -ENODATA)
718 icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);
719 icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);
725 a4xx_destroy(&a4xx_gpu->base.base);