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/linux/arch/arm/boot/dts/ti/omap/
H A Domap-zoom-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
19 reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/linux/Documentation/devicetree/bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - const: renesas,r9a06g032-sja1000 # RZ/N1D
20 - const: renesas,rzn1-sja1000 # RZ/N1
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dintel,keembay-msscam.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/intel,keembay-msscam.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
21 - const: intel,keembay-msscam
22 - const: syscon
27 reg-io-width:
31 - compatible
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/linux/arch/sh/include/mach-se/mach/
H A Dmrshpc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/io.h>
19 * PC-Card window open in mrshpc_setup_windows()
20 * flag == COMMON/ATTRIBUTE/IO in mrshpc_setup_windows()
25 /* common mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
34 /* attribute mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
37 /* attribute mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
44 __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
46 __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
/linux/arch/arc/boot/dts/
H A Dvdk_axs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&mb_intc>;
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 #clock-cells = <0>;
24 compatible = "fixed-clock";
[all …]
/linux/include/video/
H A Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Depson,rtc7301.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Epson Toyocom RTC-7301SF/DG
15 - Akinobu Mita <akinobu.mita@gmail.com>
20 - epson,rtc7301dg
21 - epson,rtc7301sf
26 reg-io-width:
28 The size (in bytes) of the IO accesses that should be performed
37 - compatible
[all …]
/linux/drivers/irqchip/
H A Dirq-renesas-intc-irqpin.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/io.h>
35 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
36 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
37 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
38 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 * (*) May be accessed by more than one driver instance - lock needed
42 * (**) Read-modify-write access by one driver instance - lock needed
43 * (***) Accessed by one driver instance only - no locking needed
[all …]
/linux/tools/perf/Documentation/
H A Dperf-timechart.txt1 perf-timechart(1)
5 ----
6 perf-timechart - Tool to visualize total system behavior during a workload
9 ---
[all...]
/linux/arch/arm64/boot/dts/bitmain/
H A Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/linux/lib/
H A Dtrace_readwrite.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
10 #include <linux/io.h>
16 void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr, in log_write_mmio() argument
19 trace_rwmmio_write(caller_addr, caller_addr0, val, width, addr); in log_write_mmio()
24 void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr, in log_post_write_mmio() argument
27 trace_rwmmio_post_write(caller_addr, caller_addr0, val, width, addr); in log_post_write_mmio()
32 void log_read_mmio(u8 width, const volatile void __iomem *addr, in log_read_mmio() argument
35 trace_rwmmio_read(caller_addr, caller_addr0, width, addr); in log_read_mmio()
40 void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr, in log_post_read_mmio() argument
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsmsc,lan91c111.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
10 - Nicolas Pitre <nico@fluxnic.net>
13 - $ref: ethernet-controller.yaml#
25 reg-shift: true
27 reg-io-width:
31 reset-gpios:
35 power-gpios:
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
[all …]
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
[all …]
/linux/arch/arm/mach-s3c/
H A Dsetup-sdhci-gpio-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0
7 // S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
13 #include <linux/io.h>
16 #include "gpio-cfg.h"
18 #include "gpio-samsung.h"
20 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) in s3c64xx_setup_sdhci0_cfg_gpio() argument
22 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; in s3c64xx_setup_sdhci0_cfg_gpio()
24 /* Set all the necessary GPG pins to special-function 2 */ in s3c64xx_setup_sdhci0_cfg_gpio()
25 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); in s3c64xx_setup_sdhci0_cfg_gpio()
27 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { in s3c64xx_setup_sdhci0_cfg_gpio()
[all …]
/linux/drivers/memory/samsung/
H A Dexynos-srom.c1 // SPDX-License-Identifier: GPL-2.0
6 // Exynos - SROM Controller support
9 #include <linux/io.h>
17 #include "exynos-srom.h"
70 u32 bank, width, pmc = 0; in exynos_srom_configure_bank() local
75 return -EINVAL; in exynos_srom_configure_bank()
76 if (of_property_read_u32(np, "reg-io-width", &width)) in exynos_srom_configure_bank()
77 width = 1; in exynos_srom_configure_bank()
78 if (of_property_read_bool(np, "samsung,srom-page-mode")) in exynos_srom_configure_bank()
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
[all …]
/linux/drivers/tty/serial/
H A Dserial_port.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
27 !kfifo_is_empty(&port->state->port.xmit_fifo); in __serial_port_busy()
36 port = port_dev->port; in serial_port_runtime_resume()
38 if (port->flags & UPF_DEAD) in serial_port_runtime_resume()
43 if (!port_dev->tx_enabled) in serial_port_runtime_resume()
46 port->ops->start_tx(port); in serial_port_runtime_resume()
60 struct uart_port *port = port_dev->port; in serial_port_runtime_suspend()
64 if (port->flags & UPF_DEAD) in serial_port_runtime_suspend()
75 if (!port_dev->tx_enabled) { in serial_port_runtime_suspend()
[all …]
/linux/drivers/clk/mxs/
H A Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
8 #include <linux/io.h>
13 * struct clk_frac - mxs fractional divider clock
17 * @width: the divider bit width
27 u8 width; member
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
44 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
51 unsigned long parent_rate = req->best_parent_rate; in clk_frac_determine_rate()
[all …]
/linux/arch/arm/mach-sa1100/
H A Djornada720.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/jornada720.c
17 #include <linux/platform_data/sa11x0-serial.h>
26 #include <asm/mach-types.h>
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
73 {0x0032,0x4F}, // LCD Horizontal Display Width Register
74 {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
[all …]

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