Lines Matching +full:io +full:- +full:width

4  * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
28 #define S1DREG_GPIO_CNF0		0x0004	/* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1		0x0005	/* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0		0x0008	/* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1		0x0009	/* General IO Pins Control Register 1 */
44 #define S1DREG_LCD_DISP_HWIDTH		0x0032	/* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER		0x0034	/* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH	0x0036	/* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER		0x003A	/* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH	0x003C	/* TFT FPFRAME Pulse Width Register */
63 #define S1DREG_CRT_DISP_HWIDTH		0x0050	/* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER		0x0052	/* CRT/TV Horizontal Non-Display Period Register */
66 #define S1DREG_CRT_HRTC_PWIDTH		0x0054	/* CRT/TV HRTC Pulse Width Register */
69 #define S1DREG_CRT_NDISP_VPER		0x0058	/* CRT/TV Vertical Non-Display Period Register */
71 #define S1DREG_CRT_VRTC_PWIDTH		0x005A	/* CRT/TV VRTC Pulse Width Register */
120 #define S1DREG_BBLT_WIDTH0		0x0110	/* BitBLT Width Register 0 */
121 #define S1DREG_BBLT_WIDTH1		0x0111	/* BitBLT Width Register 1 */
128 #define S1DREG_LKUP_MODE		0x01E0	/* Look-Up Table Mode Register */
129 #define S1DREG_LKUP_ADDR		0x01E2	/* Look-Up Table Address Register */
130 #define S1DREG_LKUP_DATA		0x01E4	/* Look-Up Table Data Register */
133 #define S1DREG_CPU2MEM_WDOGT		0x01F4	/* CPU-to-Memory Access Watchdog Timer Register */