1*4985a545SJulius Werner# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4985a545SJulius Werner%YAML 1.2 3*4985a545SJulius Werner--- 4*4985a545SJulius Werner$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# 5*4985a545SJulius Werner$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4985a545SJulius Werner 7*4985a545SJulius Wernertitle: LPDDR channel with chip/rank topology description 8*4985a545SJulius Werner 9*4985a545SJulius Wernerdescription: 10*4985a545SJulius Werner An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, 11*4985a545SJulius Werner CK, etc.) that connect one or more LPDDR chips to a host system. The main 12*4985a545SJulius Werner purpose of this node is to overall LPDDR topology of the system, including the 13*4985a545SJulius Werner amount of individual LPDDR chips and the ranks per chip. 14*4985a545SJulius Werner 15*4985a545SJulius Wernermaintainers: 16*4985a545SJulius Werner - Julius Werner <jwerner@chromium.org> 17*4985a545SJulius Werner 18*4985a545SJulius Wernerproperties: 19*4985a545SJulius Werner compatible: 20*4985a545SJulius Werner enum: 21*4985a545SJulius Werner - jedec,lpddr2-channel 22*4985a545SJulius Werner - jedec,lpddr3-channel 23*4985a545SJulius Werner - jedec,lpddr4-channel 24*4985a545SJulius Werner - jedec,lpddr5-channel 25*4985a545SJulius Werner 26*4985a545SJulius Werner io-width: 27*4985a545SJulius Werner description: 28*4985a545SJulius Werner The number of DQ pins in the channel. If this number is different 29*4985a545SJulius Werner from (a multiple of) the io-width of the LPDDR chip, that means that 30*4985a545SJulius Werner multiple instances of that type of chip are wired in parallel on this 31*4985a545SJulius Werner channel (with the channel's DQ pins split up between the different 32*4985a545SJulius Werner chips, and the CA, CS, etc. pins of the different chips all shorted 33*4985a545SJulius Werner together). This means that the total physical memory controlled by a 34*4985a545SJulius Werner channel is equal to the sum of the densities of each rank on the 35*4985a545SJulius Werner connected LPDDR chip, times the io-width of the channel divided by 36*4985a545SJulius Werner the io-width of the LPDDR chip. 37*4985a545SJulius Werner enum: 38*4985a545SJulius Werner - 8 39*4985a545SJulius Werner - 16 40*4985a545SJulius Werner - 32 41*4985a545SJulius Werner - 64 42*4985a545SJulius Werner - 128 43*4985a545SJulius Werner 44*4985a545SJulius Werner "#address-cells": 45*4985a545SJulius Werner const: 1 46*4985a545SJulius Werner 47*4985a545SJulius Werner "#size-cells": 48*4985a545SJulius Werner const: 0 49*4985a545SJulius Werner 50*4985a545SJulius WernerpatternProperties: 51*4985a545SJulius Werner "^rank@[0-9]+$": 52*4985a545SJulius Werner type: object 53*4985a545SJulius Werner description: 54*4985a545SJulius Werner Each physical LPDDR chip may have one or more ranks. Ranks are 55*4985a545SJulius Werner internal but fully independent sub-units of the chip. Each LPDDR bus 56*4985a545SJulius Werner transaction on the channel targets exactly one rank, based on the 57*4985a545SJulius Werner state of the CS pins. Different ranks may have different densities and 58*4985a545SJulius Werner timing requirements. 59*4985a545SJulius Werner required: 60*4985a545SJulius Werner - reg 61*4985a545SJulius Werner 62*4985a545SJulius WernerallOf: 63*4985a545SJulius Werner - if: 64*4985a545SJulius Werner properties: 65*4985a545SJulius Werner compatible: 66*4985a545SJulius Werner contains: 67*4985a545SJulius Werner const: jedec,lpddr2-channel 68*4985a545SJulius Werner then: 69*4985a545SJulius Werner patternProperties: 70*4985a545SJulius Werner "^rank@[0-9]+$": 71*4985a545SJulius Werner $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# 72*4985a545SJulius Werner - if: 73*4985a545SJulius Werner properties: 74*4985a545SJulius Werner compatible: 75*4985a545SJulius Werner contains: 76*4985a545SJulius Werner const: jedec,lpddr3-channel 77*4985a545SJulius Werner then: 78*4985a545SJulius Werner patternProperties: 79*4985a545SJulius Werner "^rank@[0-9]+$": 80*4985a545SJulius Werner $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# 81*4985a545SJulius Werner - if: 82*4985a545SJulius Werner properties: 83*4985a545SJulius Werner compatible: 84*4985a545SJulius Werner contains: 85*4985a545SJulius Werner const: jedec,lpddr4-channel 86*4985a545SJulius Werner then: 87*4985a545SJulius Werner patternProperties: 88*4985a545SJulius Werner "^rank@[0-9]+$": 89*4985a545SJulius Werner $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# 90*4985a545SJulius Werner - if: 91*4985a545SJulius Werner properties: 92*4985a545SJulius Werner compatible: 93*4985a545SJulius Werner contains: 94*4985a545SJulius Werner const: jedec,lpddr5-channel 95*4985a545SJulius Werner then: 96*4985a545SJulius Werner patternProperties: 97*4985a545SJulius Werner "^rank@[0-9]+$": 98*4985a545SJulius Werner $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# 99*4985a545SJulius Werner 100*4985a545SJulius Wernerrequired: 101*4985a545SJulius Werner - compatible 102*4985a545SJulius Werner - io-width 103*4985a545SJulius Werner - "#address-cells" 104*4985a545SJulius Werner - "#size-cells" 105*4985a545SJulius Werner 106*4985a545SJulius WerneradditionalProperties: false 107*4985a545SJulius Werner 108*4985a545SJulius Wernerexamples: 109*4985a545SJulius Werner - | 110*4985a545SJulius Werner lpddr-channel0 { 111*4985a545SJulius Werner #address-cells = <1>; 112*4985a545SJulius Werner #size-cells = <0>; 113*4985a545SJulius Werner compatible = "jedec,lpddr3-channel"; 114*4985a545SJulius Werner io-width = <32>; 115*4985a545SJulius Werner 116*4985a545SJulius Werner rank@0 { 117*4985a545SJulius Werner compatible = "lpddr3-ff,0100", "jedec,lpddr3"; 118*4985a545SJulius Werner reg = <0>; 119*4985a545SJulius Werner density = <8192>; 120*4985a545SJulius Werner io-width = <16>; 121*4985a545SJulius Werner revision-id = <1 0>; 122*4985a545SJulius Werner }; 123*4985a545SJulius Werner }; 124*4985a545SJulius Werner 125*4985a545SJulius Werner lpddr-channel1 { 126*4985a545SJulius Werner #address-cells = <1>; 127*4985a545SJulius Werner #size-cells = <0>; 128*4985a545SJulius Werner compatible = "jedec,lpddr4-channel"; 129*4985a545SJulius Werner io-width = <32>; 130*4985a545SJulius Werner 131*4985a545SJulius Werner rank@0 { 132*4985a545SJulius Werner compatible = "lpddr4-05,0301", "jedec,lpddr4"; 133*4985a545SJulius Werner reg = <0>; 134*4985a545SJulius Werner density = <4096>; 135*4985a545SJulius Werner io-width = <32>; 136*4985a545SJulius Werner revision-id = <3 1>; 137*4985a545SJulius Werner }; 138*4985a545SJulius Werner 139*4985a545SJulius Werner rank@1 { 140*4985a545SJulius Werner compatible = "lpddr4-05,0301", "jedec,lpddr4"; 141*4985a545SJulius Werner reg = <1>; 142*4985a545SJulius Werner density = <2048>; 143*4985a545SJulius Werner io-width = <32>; 144*4985a545SJulius Werner revision-id = <3 1>; 145*4985a545SJulius Werner }; 146*4985a545SJulius Werner }; 147