Lines Matching +full:io +full:- +full:width
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
29 from (a multiple of) the io-width of the LPDDR chip, that means that
35 connected LPDDR chip, times the io-width of the channel divided by
36 the io-width of the LPDDR chip.
38 - 8
39 - 16
40 - 32
41 - 64
42 - 128
44 "#address-cells":
47 "#size-cells":
51 "^rank@[0-9]+$":
55 internal but fully independent sub-units of the chip. Each LPDDR bus
60 - reg
63 - if:
67 const: jedec,lpddr2-channel
70 "^rank@[0-9]+$":
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
72 - if:
76 const: jedec,lpddr3-channel
79 "^rank@[0-9]+$":
80 $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
81 - if:
85 const: jedec,lpddr4-channel
88 "^rank@[0-9]+$":
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
90 - if:
94 const: jedec,lpddr5-channel
97 "^rank@[0-9]+$":
98 $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
101 - compatible
102 - io-width
103 - "#address-cells"
104 - "#size-cells"
109 - |
110 lpddr-channel0 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 compatible = "jedec,lpddr3-channel";
114 io-width = <32>;
117 compatible = "lpddr3-ff,0100", "jedec,lpddr3";
120 io-width = <16>;
121 revision-id = <1 0>;
125 lpddr-channel1 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "jedec,lpddr4-channel";
129 io-width = <32>;
132 compatible = "lpddr4-05,0301", "jedec,lpddr4";
135 io-width = <32>;
136 revision-id = <3 1>;
140 compatible = "lpddr4-05,0301", "jedec,lpddr4";
143 io-width = <32>;
144 revision-id = <3 1>;