/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Exynos5410 SoC pin-mux and pin-config device tree source 9 #include "exynos-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 16 interrupt-controller; 17 #interrupt-cells = <2>; 20 gpa1: gpa1-gpio-bank { 21 gpio-controller; [all …]
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H A D | exynos5260-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpa1: gpa1-gpio-bank { [all …]
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H A D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpa1: gpa1-gpio-bank { [all …]
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H A D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 gpy7: gpy7-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 #interrupt-cells = <2>; 23 gpx0: gpx0-gpio-bank { [all …]
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H A D | exynos4x12-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ 18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ 22 gpa0: gpa0-gpio-bank { 23 gpio-controller; 24 #gpio-cells = <2>; [all …]
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/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | via,vt8500-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: VIA and WonderMedia SoCs Interrupt Controller 10 This is the interrupt controller used in single-core ARM SoCs made by 12 up to 64 interrupt sources (level or edge triggered) and can generate 16 - Alexey Charkov <alchark@gmail.com> 19 - $ref: /schemas/interrupt-controller.yaml# 23 const: via,vt8500-intc [all …]
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H A D | samsung,exynos4210-combiner.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung Exynos SoC Interrupt Combiner Controller 10 - Krzysztof Kozlowski <krzk@kernel.org> 13 Samsung's Exynos4 architecture includes a interrupt combiner controller which 14 can combine interrupt sources as a group and provide a single interrupt 15 request for the group. The interrupt request from each group are connected to 16 a parent interrupt controller, such as GIC in case of Exynos4210. [all …]
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H A D | snps,dw-apb-ictl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Synopsys DesignWare APB interrupt controller 10 - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 11 - Zhen Lei <thunder.leizhen@huawei.com> 14 Synopsys DesignWare provides interrupt controller IP for APB known as 15 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs 17 interrupt controller in some SoCs, e.g. Hisilicon SD5203. [all …]
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H A D | interrupts.txt | 1 Specifying interrupt information for devices 4 1) Interrupt client nodes 5 ------------------------- 8 "interrupts" property, an "interrupts-extended" property, or both. If both are 11 properties contain a list of interrupt specifiers, one per output interrupt. The 12 format of the interrupt specifier is determined by the interrupt controller to 16 interrupt-parent = <&intc1>; 19 The "interrupt-parent" property is used to specify the controller to which 20 interrupts are routed and contains a single phandle referring to the interrupt 21 controller node. This property is inherited, so it may be specified in an [all …]
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H A D | mti,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MIPS Global Interrupt Controller 10 - Paul Burton <paulburton@kernel.org> 11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de> 15 It also supports local (per-processor) interrupts and software-generated 16 interrupts which can be used as IPIs. The GIC also includes a free-running 17 global timer, per-CPU count/compare timers, and a watchdog. [all …]
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H A D | marvell,ap806-sei.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Marvell SEI (System Error Interrupt) Controller 10 - Miquel Raynal <miquel.raynal@bootlin.com> 13 Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It 15 interrupt line (an SPI) on the parent interrupt controller. 17 This interrupt controller can handle up to 64 SEIs, a set comes from the AP 22 const: marvell,ap806-sei [all …]
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H A D | ti,pruss-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI PRU-ICSS Local Interrupt Controller 10 - Suman Anna <s-anna@ti.com> 13 Each PRU-ICSS has a single interrupt controller instance that is common 14 to all the PRU cores. Most interrupt controllers can route 64 input events 19 remaining 8 (2 through 9) connected to external interrupt controllers 22 The property "ti,irqs-reserved" is used for denoting the connection [all …]
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H A D | marvell,mpic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller 10 - Marek Behún <kabel@kernel.org> 13 The top-level interrupt controller on Marvell Armada 370 and XP. On these 14 platforms it also provides inter-processor interrupts. 16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC. 26 - description: main registers [all …]
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/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos7-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as 12 #include "exynos-pinctrl.h" 15 gpa0: gpa0-gpio-bank { 16 gpio-controller; 17 #gpio-cells = <2>; 19 interrupt-controller; 20 interrupt-parent = <&gic>; 21 #interrupt-cells = <2>; [all …]
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H A D | exynos5433-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \ 32 gpa0: gpa0-gpio-bank { 33 gpio-controller; [all …]
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H A D | exynos850-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "exynos-pinctrl.h" 16 gpa0: gpa0-gpio-bank { 17 gpio-controller; 18 #gpio-cells = <2>; 20 interrupt-controller; 21 #interrupt-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2021 Tesla, Inc. 11 #include "fsd-pinctrl.h" 14 gpf0: gpf0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 18 interrupt-controller; 19 #interrupt-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/exynos/google/ |
H A D | gs101-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * GS101 SoC pin-mux and pin-config device tree source 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 9 #include "gs101-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 15 interrupt-controller; 16 #interrupt-cells = <2>; [all …]
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/linux/arch/arm64/boot/dts/hisilicon/ |
H A D | hi3670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/hi3670-clock.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "arm,psci-0.2"; 24 #address-cells = <2>; 25 #size-cells = <0>; 27 cpu-map { [all …]
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/linux/arch/mips/boot/dts/loongson/ |
H A D | loongson1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com> 6 /dts-v1/; 8 #include <dt-bindings/clock/loongson,ls1x-clk.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 16 compatible = "fixed-clock"; 17 clock-output-names = "xtal"; 18 #clock-cells = <0>; [all …]
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/linux/Documentation/devicetree/bindings/pci/ |
H A D | xlnx,nwl-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 18 const: xlnx,nwl-pcie-2.11 22 - description: PCIe bridge registers location. 23 - description: PCIe Controller registers location. [all …]
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/linux/arch/mips/boot/dts/brcm/ |
H A D | bcm7358.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <375000000>; 24 cpu_intc: interrupt-controller { 25 #address-cells = <0>; 26 compatible = "mti,cpu-interrupt-controller"; 28 interrupt-controller; [all …]
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/linux/arch/arm64/boot/dts/nuvoton/ |
H A D | ma35d1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 * Author: Shan-Chun Hung <schung@nuvoton.com> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 12 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; [all …]
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/linux/arch/arc/boot/dts/ |
H A D | abilis_tb101.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 15 bus-frequency = <166666666>; 18 clock-frequency = <1000000000>; 21 clock-mult = <1>; 22 clock-div = <2>; 25 clock-mult = <1>; 26 clock-div = <6>; 31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */ 34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */ 37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */ [all …]
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H A D | abilis_tb100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 15 bus-frequency = <166666666>; 18 clock-frequency = <1000000000>; 21 clock-mult = <1>; 22 clock-div = <2>; 25 clock-mult = <1>; 26 clock-div = <6>; 31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */ 34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */ 37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */ [all …]
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