| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_memirq.c | 1 // SPDX-License-Identifier: MIT
25 drm_##_level(&memirq_to_xe(m)->drm, "MEMIRQ%u: " _fmt, \
26 memirq_to_tile(m)->id, ##__VA_ARGS__)
54 * DOC: Memory Based Interrupts
56 * MMIO register based interrupts infrastructure used for non-virtualized mode
57 * or SRIOV-8 (which supports 8 Virtual Functions) does not scale efficiently
59 * containers. Memory based interrupt status reporting provides an efficient
62 * For memory based interrupt status reporting hardware sequence is:
63 * * Engine writes the interrupt event to memory
65 * be mapped to system memory and must be marked as un-cacheable (UC) on
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | marvell-bt-8xxx.txt | 1 Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based)
2 ------
9 - compatible : should be one of the following:
10 * "marvell,sd8897-bt" (for SDIO)
11 * "marvell,sd8997-bt" (for SDIO)
16 - marvell,cal-data: Calibration data downloaded to the device during
20 - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
22 - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host
25 - interrupt-names: Used only for USB based devices (See below)
26 - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the
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| H A D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| H A D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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| /linux/Documentation/timers/ |
| H A D | highres.rst | 8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
40 - time ordered enqueueing into a rb-tree
41 - independent of ticks (the processing is based on nanoseconds)
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | e1000.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
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|
| H A D | e1000e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
52 Interrupt Throttle Rate controls the number of interrupts each interrupt
58 per second, even if more packets have come in. This reduces interrupt
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| /linux/Documentation/arch/arm/ |
| H A D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
34 SA1111 and another comes in, you have to wait for that interrupt to
35 finish processing before you can service the new interrupt. Eg, an
36 IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | rockchip-dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
22 - description: AHB clock for PCIe master
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| H A D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
17 snps,dw-pcie.yaml.
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| /linux/Documentation/devicetree/bindings/serial/ |
| H A D | brcm,bcm7271-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom 8250 based serial port
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
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| /linux/drivers/watchdog/ |
| H A D | at91sam9_wdt.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Watchdog Timer (WDT) - System peripherals regsters.
10 * Based on AT91SAM9261 datasheet revision D.
11 * Based on SAM9X60 datasheet.
29 #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */
52 /* Interrupt Enable Register */
54 /* Period Interrupt Enable */
56 /* Interrupt Disable Register */
58 /* Interrupt Status Register */
|
| /linux/drivers/iio/trigger/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 menu "Triggers - standalone"
13 Provides a frequency based IIO trigger using high resolution
14 timers as interrupt source.
17 module will be called iio-trig-hrtimer.
20 tristate "Generic interrupt trigger"
22 Provides support for using an interrupt of any type as an IIO
26 module will be called iio-trig-interrupt.
29 tristate "STM32 Low-Power Timer Trigger"
32 Select this option to enable STM32 Low-Power Timer Trigger.
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| /linux/drivers/net/can/sja1000/ |
| H A D | plx_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
13 #include <linux/interrupt.h>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
37 /* Pointer to device-dependent reset function */
44 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */
50 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
51 #define PLX_LINT1_POL (1 << 1) /* Local interrupt 1 polarity */
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| /linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | bq24257.yaml | 1 # SPDX-License-Identifier: GPL-2.0
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Bq24250, bq24251 and bq24257 Li-Ion Charger
11 - Sebastian Reichel <sre@kernel.org>
14 - $ref: power-supply.yaml#
19 - ti,bq24250
20 - ti,bq24251
21 - ti,bq24257
29 ti,battery-regulation-voltage:
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| /linux/Documentation/scsi/ |
| H A D | hptiop.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 -----------------------
11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
28 0x24 Inbound Interrupt Status Register
29 0x28 Inbound Interrupt Mask Register
30 0x30 Outbound Interrupt Status Register
31 0x34 Outbound Interrupt Mask Register
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
46 0x24 Inbound Interrupt Status Register
47 0x28 Inbound Interrupt Mask Register
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| /linux/Documentation/networking/ |
| H A D | scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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| /linux/arch/mips/pci/ |
| H A D | msi-octeon.c | 6 * Copyright (C) 2005-2009, 2010 Cavium Networks
12 #include <linux/interrupt.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
49 * arch_setup_msi_irq() - setup MSI IRQs for a device
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| /linux/Documentation/devicetree/bindings/ |
| H A D | writing-bindings.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 Documentation/devicetree/bindings/submitting-patches.rst
17 - DO attempt to make bindings complete even if a driver doesn't support some
18 features. For example, if a device has an interrupt, then include the
21 - DON'T refer to Linux or "device driver" in bindings. Bindings should be
22 based on what the hardware has, not what an OS and driver currently support.
24 - DO use node names matching the class of the device. Many standard names are
27 - DO check that the example matches the documentation especially after making
30 - DON'T create nodes just for the sake of instantiating drivers. Multi-function
34 - DON'T use 'syscon' alone without a specific compatible string. A 'syscon'
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| /linux/arch/alpha/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
43 The Alpha is a 64-bit general-purpose processor designed and
45 now Hewlett-Packard. The Alpha Linux project has a home page at
92 Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
94 LX164 AlphaPC164-LX
101 Ruffian RPX164-2, AlphaPC164-UX, AlphaPC164-BX
102 SX164 AlphaPC164-SX
119 bool "Alcor/Alpha-XLT"
122 For systems using the Digital ALCOR chipset: 5 chips (4, 64-bit data
123 slices (Data Switch, DSW) - 208-pin PQFP and 1 control (Control, I/O
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
8 based SoCs
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | gateworks-gsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Watchdog Timer
15 - GPIO
16 - Pushbutton controller
17 - Hardware monitor with ADC's for temperature and voltage rails and
21 - Tim Harvey <tharvey@gateworks.com>
25 pattern: "gsc@[0-9a-f]{1,2}"
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| /linux/Documentation/arch/x86/ |
| H A D | kernel-stacks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Kernel stacks on x86-64 bit
25 * Interrupt stack. IRQ_STACK_SIZE
28 hardware interrupt (i.e. not a nested hardware interrupt) then the
29 kernel switches from the current task to the interrupt stack. Like
30 the split thread and interrupt stacks on i386, this gives more room
31 for kernel interrupt processing without having to increase the size
34 The interrupt stack is also used when processing a softirq.
36 Switching to the kernel interrupt stack is done by software based on a
37 per CPU interrupt nest counter. This is needed because x86-64 "IST"
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| /linux/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-v3.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
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| /linux/drivers/irqchip/ |
| H A D | irq-al-fic.c | 1 // SPDX-License-Identifier: GPL-2.0
28 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
75 ret = -EINVAL; in al_fic_irq_set_type()
87 * We configure it based on the sensitivity of the first source in al_fic_irq_set_type()
91 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
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