1*e790a4ceSJonathan Corbet========== 2*e790a4ceSJonathan CorbetInterrupts 3*e790a4ceSJonathan Corbet========== 4*e790a4ceSJonathan Corbet 5*e790a4ceSJonathan Corbet2.5.2-rmk5: 6*e790a4ceSJonathan Corbet This is the first kernel that contains a major shake up of some of the 7*e790a4ceSJonathan Corbet major architecture-specific subsystems. 8*e790a4ceSJonathan Corbet 9*e790a4ceSJonathan CorbetFirstly, it contains some pretty major changes to the way we handle the 10*e790a4ceSJonathan CorbetMMU TLB. Each MMU TLB variant is now handled completely separately - 11*e790a4ceSJonathan Corbetwe have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer), 12*e790a4ceSJonathan Corbetand finally TLB v4 (with write buffer, with I TLB invalidate entry). 13*e790a4ceSJonathan CorbetThere is more assembly code inside each of these functions, mainly to 14*e790a4ceSJonathan Corbetallow more flexible TLB handling for the future. 15*e790a4ceSJonathan Corbet 16*e790a4ceSJonathan CorbetSecondly, the IRQ subsystem. 17*e790a4ceSJonathan Corbet 18*e790a4ceSJonathan CorbetThe 2.5 kernels will be having major changes to the way IRQs are handled. 19*e790a4ceSJonathan CorbetUnfortunately, this means that machine types that touch the irq_desc[] 20*e790a4ceSJonathan Corbetarray (basically all machine types) will break, and this means every 21*e790a4ceSJonathan Corbetmachine type that we currently have. 22*e790a4ceSJonathan Corbet 23*e790a4ceSJonathan CorbetLets take an example. On the Assabet with Neponset, we have:: 24*e790a4ceSJonathan Corbet 25*e790a4ceSJonathan Corbet GPIO25 IRR:2 26*e790a4ceSJonathan Corbet SA1100 ------------> Neponset -----------> SA1111 27*e790a4ceSJonathan Corbet IIR:1 28*e790a4ceSJonathan Corbet -----------> USAR 29*e790a4ceSJonathan Corbet IIR:0 30*e790a4ceSJonathan Corbet -----------> SMC9196 31*e790a4ceSJonathan Corbet 32*e790a4ceSJonathan CorbetThe way stuff currently works, all SA1111 interrupts are mutually 33*e790a4ceSJonathan Corbetexclusive of each other - if you're processing one interrupt from the 34*e790a4ceSJonathan CorbetSA1111 and another comes in, you have to wait for that interrupt to 35*e790a4ceSJonathan Corbetfinish processing before you can service the new interrupt. Eg, an 36*e790a4ceSJonathan CorbetIDE PIO-based interrupt on the SA1111 excludes all other SA1111 and 37*e790a4ceSJonathan CorbetSMC9196 interrupts until it has finished transferring its multi-sector 38*e790a4ceSJonathan Corbetdata, which can be a long time. Note also that since we loop in the 39*e790a4ceSJonathan CorbetSA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely. 40*e790a4ceSJonathan Corbet 41*e790a4ceSJonathan Corbet 42*e790a4ceSJonathan CorbetThe new approach brings several new ideas... 43*e790a4ceSJonathan Corbet 44*e790a4ceSJonathan CorbetWe introduce the concept of a "parent" and a "child". For example, 45*e790a4ceSJonathan Corbetto the Neponset handler, the "parent" is GPIO25, and the "children"d 46*e790a4ceSJonathan Corbetare SA1111, SMC9196 and USAR. 47*e790a4ceSJonathan Corbet 48*e790a4ceSJonathan CorbetWe also bring the idea of an IRQ "chip" (mainly to reduce the size of 49*e790a4ceSJonathan Corbetthe irqdesc array). This doesn't have to be a real "IC"; indeed the 50*e790a4ceSJonathan CorbetSA11x0 IRQs are handled by two separate "chip" structures, one for 51*e790a4ceSJonathan CorbetGPIO0-10, and another for all the rest. It is just a container for 52*e790a4ceSJonathan Corbetthe various operations (maybe this'll change to a better name). 53*e790a4ceSJonathan CorbetThis structure has the following operations:: 54*e790a4ceSJonathan Corbet 55*e790a4ceSJonathan Corbet struct irqchip { 56*e790a4ceSJonathan Corbet /* 57*e790a4ceSJonathan Corbet * Acknowledge the IRQ. 58*e790a4ceSJonathan Corbet * If this is a level-based IRQ, then it is expected to mask the IRQ 59*e790a4ceSJonathan Corbet * as well. 60*e790a4ceSJonathan Corbet */ 61*e790a4ceSJonathan Corbet void (*ack)(unsigned int irq); 62*e790a4ceSJonathan Corbet /* 63*e790a4ceSJonathan Corbet * Mask the IRQ in hardware. 64*e790a4ceSJonathan Corbet */ 65*e790a4ceSJonathan Corbet void (*mask)(unsigned int irq); 66*e790a4ceSJonathan Corbet /* 67*e790a4ceSJonathan Corbet * Unmask the IRQ in hardware. 68*e790a4ceSJonathan Corbet */ 69*e790a4ceSJonathan Corbet void (*unmask)(unsigned int irq); 70*e790a4ceSJonathan Corbet /* 71*e790a4ceSJonathan Corbet * Re-run the IRQ 72*e790a4ceSJonathan Corbet */ 73*e790a4ceSJonathan Corbet void (*rerun)(unsigned int irq); 74*e790a4ceSJonathan Corbet /* 75*e790a4ceSJonathan Corbet * Set the type of the IRQ. 76*e790a4ceSJonathan Corbet */ 77*e790a4ceSJonathan Corbet int (*type)(unsigned int irq, unsigned int, type); 78*e790a4ceSJonathan Corbet }; 79*e790a4ceSJonathan Corbet 80*e790a4ceSJonathan Corbetack 81*e790a4ceSJonathan Corbet - required. May be the same function as mask for IRQs 82*e790a4ceSJonathan Corbet handled by do_level_IRQ. 83*e790a4ceSJonathan Corbetmask 84*e790a4ceSJonathan Corbet - required. 85*e790a4ceSJonathan Corbetunmask 86*e790a4ceSJonathan Corbet - required. 87*e790a4ceSJonathan Corbetrerun 88*e790a4ceSJonathan Corbet - optional. Not required if you're using do_level_IRQ for all 89*e790a4ceSJonathan Corbet IRQs that use this 'irqchip'. Generally expected to re-trigger 90*e790a4ceSJonathan Corbet the hardware IRQ if possible. If not, may call the handler 91*e790a4ceSJonathan Corbet directly. 92*e790a4ceSJonathan Corbettype 93*e790a4ceSJonathan Corbet - optional. If you don't support changing the type of an IRQ, 94*e790a4ceSJonathan Corbet it should be null so people can detect if they are unable to 95*e790a4ceSJonathan Corbet set the IRQ type. 96*e790a4ceSJonathan Corbet 97*e790a4ceSJonathan CorbetFor each IRQ, we keep the following information: 98*e790a4ceSJonathan Corbet 99*e790a4ceSJonathan Corbet - "disable" depth (number of disable_irq()s without enable_irq()s) 100*e790a4ceSJonathan Corbet - flags indicating what we can do with this IRQ (valid, probe, 101*e790a4ceSJonathan Corbet noautounmask) as before 102*e790a4ceSJonathan Corbet - status of the IRQ (probing, enable, etc) 103*e790a4ceSJonathan Corbet - chip 104*e790a4ceSJonathan Corbet - per-IRQ handler 105*e790a4ceSJonathan Corbet - irqaction structure list 106*e790a4ceSJonathan Corbet 107*e790a4ceSJonathan CorbetThe handler can be one of the 3 standard handlers - "level", "edge" and 108*e790a4ceSJonathan Corbet"simple", or your own specific handler if you need to do something special. 109*e790a4ceSJonathan Corbet 110*e790a4ceSJonathan CorbetThe "level" handler is what we currently have - its pretty simple. 111*e790a4ceSJonathan Corbet"edge" knows about the brokenness of such IRQ implementations - that you 112*e790a4ceSJonathan Corbetneed to leave the hardware IRQ enabled while processing it, and queueing 113*e790a4ceSJonathan Corbetfurther IRQ events should the IRQ happen again while processing. The 114*e790a4ceSJonathan Corbet"simple" handler is very basic, and does not perform any hardware 115*e790a4ceSJonathan Corbetmanipulation, nor state tracking. This is useful for things like the 116*e790a4ceSJonathan CorbetSMC9196 and USAR above. 117*e790a4ceSJonathan Corbet 118*e790a4ceSJonathan CorbetSo, what's changed? 119*e790a4ceSJonathan Corbet=================== 120*e790a4ceSJonathan Corbet 121*e790a4ceSJonathan Corbet1. Machine implementations must not write to the irqdesc array. 122*e790a4ceSJonathan Corbet 123*e790a4ceSJonathan Corbet2. New functions to manipulate the irqdesc array. The first 4 are expected 124*e790a4ceSJonathan Corbet to be useful only to machine specific code. The last is recommended to 125*e790a4ceSJonathan Corbet only be used by machine specific code, but may be used in drivers if 126*e790a4ceSJonathan Corbet absolutely necessary. 127*e790a4ceSJonathan Corbet 128*e790a4ceSJonathan Corbet set_irq_chip(irq,chip) 129*e790a4ceSJonathan Corbet Set the mask/unmask methods for handling this IRQ 130*e790a4ceSJonathan Corbet 131*e790a4ceSJonathan Corbet set_irq_handler(irq,handler) 132*e790a4ceSJonathan Corbet Set the handler for this IRQ (level, edge, simple) 133*e790a4ceSJonathan Corbet 134*e790a4ceSJonathan Corbet set_irq_chained_handler(irq,handler) 135*e790a4ceSJonathan Corbet Set a "chained" handler for this IRQ - automatically 136*e790a4ceSJonathan Corbet enables this IRQ (eg, Neponset and SA1111 handlers). 137*e790a4ceSJonathan Corbet 138*e790a4ceSJonathan Corbet set_irq_flags(irq,flags) 139*e790a4ceSJonathan Corbet Set the valid/probe/noautoenable flags. 140*e790a4ceSJonathan Corbet 141*e790a4ceSJonathan Corbet set_irq_type(irq,type) 142*e790a4ceSJonathan Corbet Set active the IRQ edge(s)/level. This replaces the 143*e790a4ceSJonathan Corbet SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge() 144*e790a4ceSJonathan Corbet function. Type should be one of IRQ_TYPE_xxx defined in 145*e790a4ceSJonathan Corbet <linux/irq.h> 146*e790a4ceSJonathan Corbet 147*e790a4ceSJonathan Corbet3. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type. 148*e790a4ceSJonathan Corbet 149*e790a4ceSJonathan Corbet4. Direct access to SA1111 INTPOL is deprecated. Use set_irq_type instead. 150*e790a4ceSJonathan Corbet 151*e790a4ceSJonathan Corbet5. A handler is expected to perform any necessary acknowledgement of the 152*e790a4ceSJonathan Corbet parent IRQ via the correct chip specific function. For instance, if 153*e790a4ceSJonathan Corbet the SA1111 is directly connected to a SA1110 GPIO, then you should 154*e790a4ceSJonathan Corbet acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status. 155*e790a4ceSJonathan Corbet 156*e790a4ceSJonathan Corbet6. For any child which doesn't have its own IRQ enable/disable controls 157*e790a4ceSJonathan Corbet (eg, SMC9196), the handler must mask or acknowledge the parent IRQ 158*e790a4ceSJonathan Corbet while the child handler is called, and the child handler should be the 159*e790a4ceSJonathan Corbet "simple" handler (not "edge" nor "level"). After the handler completes, 160*e790a4ceSJonathan Corbet the parent IRQ should be unmasked, and the status of all children must 161*e790a4ceSJonathan Corbet be re-checked for pending events. (see the Neponset IRQ handler for 162*e790a4ceSJonathan Corbet details). 163*e790a4ceSJonathan Corbet 164*e790a4ceSJonathan Corbet7. fixup_irq() is gone, as is `arch/arm/mach-*/include/mach/irq.h` 165*e790a4ceSJonathan Corbet 166*e790a4ceSJonathan CorbetPlease note that this will not solve all problems - some of them are 167*e790a4ceSJonathan Corbethardware based. Mixing level-based and edge-based IRQs on the same 168*e790a4ceSJonathan Corbetparent signal (eg neponset) is one such area where a software based 169*e790a4ceSJonathan Corbetsolution can't provide the full answer to low IRQ latency. 170