Lines Matching +full:interrupt +full:- +full:based
1 .. SPDX-License-Identifier: GPL-2.0
9 -----------------------
11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
28 0x24 Inbound Interrupt Status Register
29 0x28 Inbound Interrupt Mask Register
30 0x30 Outbound Interrupt Status Register
31 0x34 Outbound Interrupt Mask Register
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
46 0x24 Inbound Interrupt Status Register
47 0x28 Inbound Interrupt Mask Register
48 0x30 Outbound Interrupt Status Register
49 0x34 Outbound Interrupt Mask Register
54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
60 0x20404 Inbound Interrupt Mask Register
62 0x2040C Outbound Interrupt Mask Register
74 0x40-0x1040 Inbound Queue
75 0x1040-0x2040 Outbound Queue
78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
97 0x4088 Outbound List Interrupt Cause
98 0x408C Outbound List Interrupt Enable
99 0x1020C PCIe Function 0 Interrupt Enable
108 ----------------------------------------
115 - Get a free request packet by reading the inbound queue port or
121 Requests allocated in host memory must be aligned on 32-bytes boundary.
123 - Fill the packet.
125 - Post the packet to IOP by writing it to inbound queue. For requests
130 - The IOP process the request. When the request is completed, it
131 will be put into outbound queue. An outbound interrupt will be
139 flag is set in the request, the low 32-bit context value will be
142 - The host read the outbound queue and complete the request.
147 Non-queued requests (reset/flush etc) can be sent via inbound message
153 ------------------------------------
159 - Allocate a free request in host DMA coherent memory.
161 Requests allocated in host memory must be aligned on 32-bytes boundary.
163 - Fill the request with index of the request in the flag.
171 - Post the inbound list writer pointer to IOP.
173 - The IOP process the request. When the request is completed, the flag of
174 the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
176 put into the copy pointer shadow register. An outbound interrupt will be
179 - The host read the outbound list copy pointer shadow register and compare
186 Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
191 User-level Interface
192 ---------------------
199 driver-version R driver version string
200 firmware-version R firmware version string
204 -----------------------------------------------------------------------------
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213 linux@highpoint-tech.com
215 http://www.highpoint-tech.com