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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
H A Dimx7ulp-com.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include "imx7ulp.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
15 stdout-path = &lpuart4;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_lpuart4>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usbotg1_id>;
[all …]
H A Dimx7ulp-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 /dts-v1/;
10 #include "imx7ulp.dtsi"
14 compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
17 stdout-path = &lpuart4;
26 compatible = "pwm-backlight";
28 brightness-levels = <0 20 25 30 35 40 100>;
29 default-brightness-level = <6>;
33 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
[all …]
H A Dimxrt1050.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "../../armv7-m.dtsi"
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/imxrt1050-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <24000000>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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H A Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 are clocked by an asynchronous clock that can remain enabled in low
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
26 - const: fsl,imx7ulp-tpm
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
[all …]
H A Dimx8dxl-ss-adma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &asrc1;
7 /delete-node/ &asrc1_lpcg;
8 /delete-node/ &adc1;
9 /delete-node/ &adc1_lpcg;
10 /delete-node/ &amix;
11 /delete-node/ &amix_lpcg;
12 /delete-node/ &edma1;
13 /delete-node/ &esai0;
14 /delete-node/ &esai0_lpcg;
[all …]
H A Dimx8-ss-lvds1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
H A Dimx8-ss-img.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
13 img_pxl_clk: clock-img-pxl {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
[all …]
H A Dimx8-ss-lvds0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
14 compatible = "fsl,imx8qxp-lpcg";
16 #clock-cells = <1>;
17 clock-output-names = "lvds0_lis_lpcg_ipg_clk";
18 power-domains = <&pd IMX_SC_R_MIPI_1>;
21 qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
[all …]
H A Dimx8qm-ss-lvds.dtsi1 // SPDX-License-Identifier: GPL-2.0+
9 clock-indices = <IMX_LPCG_CLK_4>;
15 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
21 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
35 interrupt-parent = <&irqsteer_lvds0>;
37 irqsteer_lvds0: interrupt-controller@56240000 {
38 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
41 interrupt-controller;
42 interrupt-parent = <&gic>;
43 #interrupt-cells = <1>;
[all …]
H A Dimx8-ss-cm41.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
10 cm41_ipg_clk: clock-cm41-ipg {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <132000000>;
14 clock-output-names = "cm41_ipg_clk";
18 compatible = "simple-bus";
19 #address-cells = <1>;
[all …]
H A Dimx8-ss-cm40.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
9 cm40_ipg_clk: clock-cm40-ipg {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <132000000>;
13 clock-output-names = "cm40_ipg_clk";
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-vf610.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
23 - const: fsl,imx8ulp-gpio
24 - const: fsl,vf610-gpio
25 - items:
26 - const: fsl,imx7ulp-gpio
27 - const: fsl,vf610-gpio
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/clock/imx7ulp-clock.h>
11 #include <linux/clk-provider.h>
57 clk_data->num = IMX7ULP_CLK_SCG1_END; in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
104 /* scs/ddr/nic select different clock source requires that clock to be enabled first */ in imx7ulp_clk_scg1_init()
111 …re", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk… in imx7ulp_clk_scg1_init()
113 …IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->… in imx7ulp_clk_scg1_init()
129 imx_check_clk_hws(hws, clk_data->num); in imx7ulp_clk_scg1_init()
133 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
[all …]
/linux/arch/arm/mach-imx/
H A Dpm-imx7ulp.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
39 /* system/bus clock enabled */ in imx7ulp_set_lpm()
43 /* system clock disabled, bus clock enabled */ in imx7ulp_set_lpm()
47 /* system/bus clock disabled */ in imx7ulp_set_lpm()
51 return -EINVAL; in imx7ulp_set_lpm()
63 np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); in imx7ulp_pm_init()
/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dmmdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - const: fsl,imx6q-mmdc
18 - items:
19 - enum:
[all …]
/linux/drivers/clocksource/
H A Dtimer-imx-tpm.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "timer-of.h"
107 return (now - prev) >= delta ? -ETIME : 0; in tpm_set_next_event()
130 evt->event_handler(evt); in tpm_timer_interrupt()
167 "imx-tpm", in tpm_clocksource_init()
179 GENMASK(counter_width - 1, in tpm_clockevent_init()
191 return -ENODEV; in tpm_timer_init()
196 pr_err("tpm: ipg clock enable failed (%d)\n", ret); in tpm_timer_init()
209 /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ in tpm_timer_init()
230 * div 8 for 32-bit counter and div 128 for 16-bit counter in tpm_timer_init()
[all …]

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