| /freebsd/sbin/nvmecontrol/ |
| H A D | firmware.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
7 * Copyright (C) 2012-2013 Intel Corporation
75 "Firmware image to download"),
81 { arg_string, &opt.dev, "controller-id|namespace-i
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scif_sas_design.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
61 - Nathan Marushak
64 - Richard Boyd
71 of the SCU Software Architecture Specification, the Storage Controller
99 Some of the SAS framework objects contain sub-state machines. These
100 sub-state machines are started upon entrance to the super-state and stopped
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| H A D | sci_overview.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
58 @mainpage The Intel Storage Controller Interface (SCI)
60 SCI provides a common interface across intel storage controller hardware.
63 -# SCI Base classes
64 -# SCI Core
65 -# SCI Framework
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| /freebsd/sys/dts/powerpc/ |
| H A D | p1020rdb.dts | 35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
54 #address-cells = <1>;
55 #size-cells = <0>;
60 next-level-cache = <&L2>;
66 next-level-cache = <&L2>;
75 #address-cells = <2>;
76 #size-cells = <1>;
77 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | exynos4-fimc-is.txt | 1 Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
3 The FIMC-IS is a subsystem for processing image signal from an image sensor.
4 The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
8 fimc-is node
9 ------------
12 - compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
14 - reg : physical base address and length of the registers set;
15 - interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
16 - clocks : list of clock specifiers, corresponding to entries in
17 clock-names property;
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| H A D | fsl,imx8qxp-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8QXP Image Sensing Interface
10 - Frank Li <Frank.Li@nxp.com>
13 The Image Sensing Interface (ISI) combines image processing pipelines with
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8qxp-isi
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| H A D | fsl,imx8qm-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8QM Image Sensing Interface
10 - Frank Li <Frank.Li@nxp.com>
13 The Image Sensing Interface (ISI) combines image processing pipelines with
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8qm-isi
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|
| H A D | nxp,imx8-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8 Image Sensing Interface
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Image Sensing Interface (ISI) combines image processing pipelines with
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8mn-isi
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| H A D | raspberrypi,pispbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raspberry Pi PiSP Image Signal Processor (ISP) Back End
10 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
11 - Jacopo Mondi <jacopo.mondi@ideasonboard.com>
14 The Raspberry Pi PiSP Image Signal Processor (ISP) Back End is an image
19 https://datasheets.raspberrypi.com/camera/raspberry-pi-image-signal-processor-specification.pdf
24 - enum:
25 - brcm,bcm2712-pispbe
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| H A D | microchip,xisc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip eXtended Image Sensor Controller (XISC)
11 - Eugen Hristev <eugen.hristev@microchip.com>
14 The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
25 const: microchip,sama7g5-isc
36 clock-names:
38 - const: hclock
40 '#clock-cells':
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| H A D | samsung,exynos4212-fimc-is.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4212-fim
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| H A D | qcom,sc8280xp-camss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
17 const: qcom,sc8280xp-camss
22 clock-names:
24 - const: camnoc_axi
25 - const: cpas_ahb
26 - const: csiphy0
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| H A D | atmel,isc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright (C) 2016-2021 Microchip Technology, Inc.
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel Image Sensor Controller (ISC)
11 - Eugen Hristev <eugen.hristev@microchip.com>
14 The Image Sensor Controller (ISC) device provides the video input capabilities for the
22 const: atmel,sama5d2-isc
34 clock-names:
36 - const: hclock
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| H A D | samsung-s5c73m3.txt | 2 ------------------------------
4 The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656) video
8 and should be placed under respective bus controller nodes.
11 ---------------------
15 - compatible : "samsung,s5c73m3";
16 - reg : I2C slave address of the sensor;
17 - vdd-int-supply : digital power supply (1.2V);
18 - vdda-supply : analog power supply (1.2V);
19 - vdd-reg-supply : regulator input power supply (2.8V);
20 - vddio-host-supply : host I/O power supply (1.8V to 2.8V);
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| /freebsd/share/doc/smm/02.config/ |
| H A D | 4.t | 44 system image to be generated, and
80 \-DFUNNY \-DHAHA in the resultant makefile.
123 This is usually a cute name like ERNIE (short for Ernie Co-Vax) or
134 System image parameters
139 system specific devices may be different. A system image is specified
142 \fBconfig\fP\ \fIsysname\fP\ \fIconfig-clauses\fP
146 field is the name given to the loaded system image; almost everyone
147 names their standard system image ``kernel''. The configuration clauses
161 \fBroot\fP [ \fBon\fP ] \fIroot-device\fP
162 \fBswap\fP [ \fBon\fP ] \fIswap-device\fP [ \fBand\fP \fIswap-device\fP ] ...
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| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | fpga-region.txt | 6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
42 * A base (or static) FPGA image may create a set of PRR's that later may
45 * The connections at the edge of each PRR are fixed. The image that is loaded
52 * An FPGA image tha
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| H A D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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| /freebsd/sys/contrib/device-tree/Bindings/display/samsung/ |
| H A D | samsung,exynos5433-mic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
16 MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is
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| /freebsd/sys/contrib/device-tree/Bindings/display/hisilicon/ |
| H A D | hisi-ade.txt | 1 Device-Tree bindings for hisilicon ADE display controller driver
3 ADE (Advanced Display Engine) is the display controller which grab image
4 data from memory, do composition, do post image processing, generate RGB
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | fsl,imx8qxp-dc-blit-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Blit Engine
10 A blit operation (block based image transfer) reads up to 3 source images
11 from memory and computes one destination image from it, which is written
20 * Image Blend
24 * Image Rop2/3
28 * Image Flip
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|
| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | PciPlatform.h | 3 the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific
7 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
40 /// - EFI_RESERVE_NONE_IO_ALIAS:<BR>
46 /// - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>
49 /// ranges. In this scheme, seventy-five percent of the I/O space remains unused.
56 /// - n100..n3FF
57 /// - n500..n7FF
58 /// - n900..nBFF
59 /// - nD00..nFFF
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | c293pcie.dts | 35 /include/ "c293si-pre.dtsi"
45 ifc: memory-controller@fffe1e000 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "cfi-flash";
79 bank-width = <2>;
80 device-width = <1>;
83 /* 1MB for DTB Image */
85 label = "NOR DTB Image";
89 /* 8 MB for Linux Kernel Image */
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | stericsson,db8500-prcmu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit
10 - Linus Walleij <linus.walleij@linaro.org>
13 The DB8500 Power Reset and Control Management Unit is an XP70 8-bit
14 microprocessor that is embedded in the always-on power domain of the
20 pattern: '^prcmu@[0-9a-f]+$'
23 description: The device is compatible both to the device-specific
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| /freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | ti,k3-dsp-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
19 controller, a dedicated local power/sleep controller etc. The DSP processor
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| /freebsd/sys/contrib/edk2/Include/Uefi/ |
| H A D | UefiSpec.h | 8 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
12 SPDX-License-Identifier: BSD-2-Clause-Patent
71 // Note: UEFI spec 2.5 and following: use EFI_MEMORY_RO as write-protected physical memory
80 // The memory region supports byte-addressable non-volatility.
92 // Specific-purpose memory (SPM). The memory is earmarked for
125 // described with additional ISA-specific memory attributes
131 // Defines the bits reserved for describing optional ISA-specific cacheability
134 // See Calling Conventions for further ISA-specific enumeration of these bits.
227 @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid.
348 Connects one or more drivers to a controller.
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