Lines Matching +full:image +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Blit Engine
10 A blit operation (block based image transfer) reads up to 3 source images
11 from memory and computes one destination image from it, which is written
20 * Image Blend
24 * Image Rop2/3
28 * Image Flip
29 Mirrors the source image in horizontal and/or vertical direction.
35 Modify colors by linear or non-linear transformations.
37 * Image Scale
38 Changes size of the source image.
40 * Image Rotate
41 Rotates the source image by any angle.
43 * Image Filter
44 Performs an FIR filter operation on the source image.
46 * Image Warp
47 Performs a re-sampling of the source image with any pattern. The sample
51 Writes an image with color components stored in up to three different
59 - Liu Ying <victor.liu@nxp.com>
63 const: fsl,imx8qxp-dc-blit-engine
68 reg-names:
70 - const: pec
71 - const: cfg
73 "#address-cells":
76 "#size-cells":
82 "^blitblend@[0-9a-f]+$":
88 const: fsl,imx8qxp-dc-blitblend
90 "^clut@[0-9a-f]+$":
96 const: fsl,imx8qxp-dc-clut
98 "^fetchdecode@[0-9a-f]+$":
104 const: fsl,imx8qxp-dc-fetchdecode
106 "^fetcheco@[0-9a-f]+$":
112 const: fsl,imx8qxp-dc-fetcheco
114 "^fetchwarp@[0-9a-f]+$":
120 const: fsl,imx8qxp-dc-fetchwarp
122 "^filter@[0-9a-f]+$":
128 const: fsl,imx8qxp-dc-filter
130 "^hscaler@[0-9a-f]+$":
136 const: fsl,imx8qxp-dc-hscaler
138 "^matrix@[0-9a-f]+$":
144 const: fsl,imx8qxp-dc-matrix
146 "^rop@[0-9a-f]+$":
152 const: fsl,imx8qxp-dc-rop
154 "^store@[0-9a-f]+$":
160 const: fsl,imx8qxp-dc-store
162 "^vscaler@[0-9a-f]+$":
168 const: fsl,imx8qxp-dc-vscaler
171 - compatible
172 - reg
173 - reg-names
174 - "#address-cells"
175 - "#size-cells"
176 - ranges
181 - |
182 blit-engine@56180820 {
183 compatible = "fsl,imx8qxp-dc-blit-engine";
185 reg-names = "pec", "cfg";
186 #address-cells = <1>;
187 #size-cells = <1>;
191 compatible = "fsl,imx8qxp-dc-fetchdecode";
193 reg-names = "pec", "cfg";
197 compatible = "fsl,imx8qxp-dc-store";
199 reg-names = "pec", "cfg";
200 interrupt-parent = <&dc0_intc>;
202 interrupt-names = "shdload", "framecomplete", "seqcomplete";