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/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra186-bpmp-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) BPMP I2C controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 owns certain HW devices, such as the I2C controller for the power
16 management I2C bus. Software running on other CPUs must perform IPC to
17 the BPMP in order to execute transactions on that I2C bus. This
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H A Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3xxx I2C controller
10 This driver interfaces with the native I2C controller present in Rockchip
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
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H A Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp13-i2c
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H A Di2c-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP I2C controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
17 - mrvl,i2c-polling
20 - interrupts
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H A Di2c-owl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-owl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl I2C Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 This I2C controller is found in the Actions Semi Owl SoCs:
17 - $ref: /schemas/i2c/i2c-controller.yaml#
22 - actions,s500-i2c # Actions Semi S500 compatible SoCs
23 - actions,s700-i2c # Actions Semi S700 compatible SoCs
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H A Dbrcm,iproc-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/brcm,iproc-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc I2C controller
10 - Rafał Miłecki <rafal@milecki.pl>
15 - brcm,iproc-i2c
16 - brcm,iproc-nic-i2c
21 clock-frequency:
26 Should contain the I2C interrupt. For certain revisions of the I2C
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H A Di2c-pxa-pci-ce4100.txt1 CE4100 I2C
2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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H A Dcdns,i2c-r1p10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence I2C controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
33 clock-frequency:
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H A Dbrcm,kona-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/brcm,kona-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family I2C controller
10 - Florian Fainelli <f.fainelli@gmail.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - enum:
19 - brcm,bcm11351-i2c
20 - brcm,bcm21664-i2c
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H A Dhisilicon,ascend910-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/hisilicon,ascend910-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon common I2C controller
10 - Yicong Yang <yangyicong@hisilicon.com>
13 The HiSilicon common I2C controller can be used for many different
17 - $ref: /schemas/i2c/i2c-controller.yaml#
21 const: hisilicon,ascend910-i2c
32 clock-frequency:
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H A Dsprd,sc9860-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/sprd,sc9860-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 I2C controller
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 - $ref: /schemas/i2c/i2c-controller.yaml#
19 const: sprd,sc9860-i2c
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H A Dingenic,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/ingenic,i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs I2C controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 pattern: "^i2c@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4770-i2c
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H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
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H A Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OpenCores I2C controller
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
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H A Dhpe,gxp-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HPE GXP SoC I2C Controller
10 - Nick Hawkins <nick.hawkins@hpe.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 const: hpe,gxp-i2c
25 clock-frequency:
32 between each I2C engine controller instance. It enables the I2C
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/linux/drivers/i2c/busses/
H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/i2c.h>
21 /* Register offsets for the I2C device. */
24 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
25 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
60 * I2C Address Register Bit mask definitions
62 * bits. A write access to this register always initiates a transfer if the I2C
65 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
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H A Di2c-designware-pcidrv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
15 #include <linux/i2c.h>
27 #include "i2c-designware-core.h"
28 #include "i2c-ccgx-ucsi.h"
30 #define DRIVER_NAME "i2c-designware-pci"
91 /* NAVI-AMD HCNT/LCNT/SDA hold time */
107 switch (pdev->device) { in mfld_setup()
109 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in mfld_setup()
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H A Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
6 * I2C master mode controller driver, used in Nomadik 8815
11 * - The memory bus only supports 32-bit accesses.
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
22 #include <linux/i2c.h>
35 #define DRIVER_NAME "nmk-i2c"
37 /* I2C Controller register offsets */
72 /* Master controller (MCR) register */
74 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
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/linux/Documentation/devicetree/bindings/misc/
H A Dti,fpc202.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/ti,fpc202.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI FPC202 dual port controller with expanded IOs
10 - Romain Gantois <romain.gantois@bootlin.com>
13 - $ref: /schemas/i2c/i2c-atr.yaml#
22 gpio-controller: true
24 "#gpio-cells":
27 enable-gpios:
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/linux/Documentation/devicetree/bindings/net/
H A Dmctp-i2c-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mctp-i2c-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MCTP I2C transport
10 - Matt Johnston <matt@codeconstruct.com.au>
13 An mctp-i2c-controller defines a local MCTP endpoint on an I2C controller.
14 MCTP I2C is specified by DMTF DSP0237.
16 An mctp-i2c-controller must be attached to an I2C adapter which supports
17 slave functionality. I2C busses (either directly or as subordinate mux
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/linux/Documentation/devicetree/bindings/i3c/
H A Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i3c/i3c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
14 I3C busses can be described with a node for the primary I3C controller device
15 and a set of child nodes for each I2C or I3C slave on the bus. Each of them
20 pattern: "^i3c@[0-9a-f]+$"
22 "#address-cells":
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/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dtrivial-touch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/touchscreen/trivial-touch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Trivial touch screen controller with i2c interface
10 - Frank Li <Frank.Li@nxp.com>
16 - azoteq,iqs550
17 - azoteq,iqs572
18 - azoteq,iqs525
19 # Himax hx83100a touchscreen controller
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2400-i2c-ic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-i2c-ic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed I2C Interrupt Controller (AST24XX/AST25XX)
10 - Ryan Chen <ryan_chen@aspeedtech.com>
15 - aspeed,ast2400-i2c-ic
16 - aspeed,ast2500-i2c-ic
24 interrupt-controller: true
26 '#interrupt-cells':
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/linux/include/linux/i3c/
H A Dmaster.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/i2c.h>
39 * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
40 * @node: node element used to insert the slot into the I2C or I3C device
43 * I2C/I3C transfers
47 * This structure is describing common I3C/I2C dev information.
62 * struct i2c_dev_boardinfo - I2C device board information
63 * @node: used to insert the boardinfo object in the I2C boardinfo list
64 * @base: regular I2C board information
66 * the I2C device limitations
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