Lines Matching +full:i2c +full:- +full:controller +full:- +full:id
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
21 - description: Tegra20 has specific I2C controller called as DVC I2C
22 controller. This only support master mode of I2C communication.
24 generic I2C controller. Driver of DVC I2C controller is only
25 compatible with "nvidia,tegra20-i2c-dvc".
26 const: nvidia,tegra20-i2c-dvc
27 - description: |
28 Tegra30 has 5 generic I2C controller. This controller is very much
29 similar to Tegra20 I2C controller with additional feature: Continue
31 I2C core API transfer flags. Driver of I2C controller is compatible
32 with "nvidia,tegra30-i2c" to enable the continue transfer support.
33 This is also compatible with "nvidia,tegra20-i2c" without continue
36 - const: nvidia,tegra30-i2c
37 - const: nvidia,tegra20-i2c
38 - description: |
39 Tegra114 has 5 generic I2C controllers. This controller is very much
40 similar to Tegra30 I2C controller with some hardware modification:
41 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
42 and fast-clk. Tegra114 has only one clock source called as
43 div-clk and hence clock mechanism is changed in I2C controller.
44 - Tegra30/Tegra20 I2C controller has enabled per packet transfer
47 Due to above changes, Tegra114 I2C driver makes incompatible with
48 previous hardware driver. Hence, Tegra114 I2C controller is
49 compatible with "nvidia,tegra114-i2c".
50 const: nvidia,tegra114-i2c
51 - description: |
52 Tegra124 has 6 generic I2C controllers. These controllers are very
55 const: nvidia,tegra124-i2c
56 - description: |
57 Tegra210 has 6 generic I2C controllers. These controllers are very
60 - const: nvidia,tegra210-i2c
61 - const: nvidia,tegra124-i2c
62 - description: |
63 Tegra210 has one I2C controller that is on host1x bus and is part of
64 the VE power domain and typically used for camera use-cases. This VI
65 I2C controller is mostly compatible with the programming model of
66 the regular I2C controllers with a few exceptions. The I2C registers
68 apart (rather than 4) and the controller does not support slave
70 const: nvidia,tegra210-i2c-vi
71 - description: |
72 Tegra186 has 9 generic I2C controllers, two of which are in the AON
73 (always-on) partition of the SoC. All of these controllers are very
75 const: nvidia,tegra186-i2c
76 - description: |
77 Tegra194 has 8 generic I2C controllers, two of which are in the AON
78 (always-on) partition of the SoC. All of these controllers are very
82 const: nvidia,tegra194-i2c
94 clock-names:
100 - description: module reset
102 reset-names:
104 - const: i2c
106 power-domains:
111 - description: DMA channel for the reception FIFO
112 - description: DMA channel for the transmission FIFO
114 dma-names:
116 - const: rx
117 - const: tx
120 - $ref: /schemas/i2c/i2c-controller.yaml
121 - if:
126 - nvidia,tegra20-i2c
127 - nvidia,tegra30-i2c
132 clock-names:
134 - const: div-clk
135 - const: fast-clk
137 - if:
142 - nvidia,tegra114-i2c
143 - nvidia,tegra210-i2c
148 clock-names:
150 - const: div-clk
152 - if:
156 const: nvidia,tegra210-i2c-vi
161 clock-names:
163 - const: div-clk
164 - const: slow
165 power-domains:
167 - description: phandle to the VENC power domain
170 power-domains: false
175 - |
176 i2c@7000c000 {
177 compatible = "nvidia,tegra20-i2c";
181 clock-names = "div-clk", "fast-clk";
183 reset-names = "i2c";
185 dma-names = "rx", "tx";
187 #address-cells = <1>;
188 #size-cells = <0>;