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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrIntrinsics.inc4 {Hexagon::A2_abs, Intrinsic::hexagon_A2_abs},
5 {Hexagon::A2_absp, Intrinsic::hexagon_A2_absp},
6 {Hexagon::A2_abssat, Intrinsic::hexagon_A2_abssat},
7 {Hexagon::A2_add, Intrinsic::hexagon_A2_add},
8 {Hexagon::A2_addh_h16_hh, Intrinsic::hexagon_A2_addh_h16_hh},
9 {Hexagon::A2_addh_h16_hl, Intrinsic::hexagon_A2_addh_h16_hl},
10 {Hexagon::A2_addh_h16_lh, Intrinsic::hexagon_A2_addh_h16_lh},
11 {Hexagon::A2_addh_h16_ll, Intrinsic::hexagon_A2_addh_h16_ll},
12 {Hexagon::A2_addh_h16_sat_hh, Intrinsic::hexagon_A2_addh_h16_sat_hh},
13 {Hexagon::A2_addh_h16_sat_hl, Intrinsic::hexagon_A2_addh_h16_sat_hl},
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H A DHexagonDepTimingClasses.h20 case Hexagon::Sched::tc_112d30d6: in is_TC1()
21 case Hexagon::Sched::tc_151bf368: in is_TC1()
22 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
23 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
24 case Hexagon::Sched::tc_23708a21: in is_TC1()
25 case Hexagon::Sched::tc_24f426ab: in is_TC1()
26 case Hexagon::Sched::tc_2f573607: in is_TC1()
27 case Hexagon::Sched::tc_388f9897: in is_TC1()
28 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
29 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
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H A DHexagonInstrInfo.cpp1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
14 #include "Hexagon.h"
68 #define DEBUG_TYPE "hexagon-instrinfo"
76 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
80 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
84 "disable-hexagon-nv-schedule", cl::Hidden,
107 /// Constants for Hexagon instructions.
123 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
133 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
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H A DHexagonRegisterInfo.cpp1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
15 #include "Hexagon.h"
48 "hexagon-frame-index-search-range", cl::init(32), cl::Hidden,
52 "hexagon-frame-index-reuse-limit", cl::init(~0), cl::Hidden,
57 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
62 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || in isEHReturnCalleeSaveReg()
63 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; in isEHReturnCalleeSaveReg()
69 using namespace Hexagon; in getCallerSavedRegs()
121 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
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H A DHexagonAsmPrinter.cpp1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
16 #include "Hexagon.h"
70 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
72 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
136 if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) in PrintAsmOperand()
138 Hexagon::isub_lo : in PrintAsmOperand()
139 Hexagon::isub_hi); in PrintAsmOperand()
272 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
278 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
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H A DHexagonNewValueJump.cpp1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
9 // This implements NewValueJump pass in Hexagon.
24 #include "Hexagon.h"
55 #define DEBUG_TYPE "hexagon-nvj"
85 StringRef getPassName() const override { return "Hexagon NewValueJump"; } in getPassName()
108 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
109 "Hexagon NewValueJump", false, false)
111 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", in INITIALIZE_PASS_DEPENDENCY()
112 "Hexagon NewValueJump", false, false) in INITIALIZE_PASS_DEPENDENCY()
156 if (!Hexagon::IntRegsRegClass.contains(Op.getReg())) in INITIALIZE_PASS_DEPENDENCY()
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H A DHexagonConstExtenders.cpp28 #define DEBUG_TYPE "hexagon-cext-opt"
33 "hexagon-cext-threshold", cl::init(3), cl::Hidden,
37 ReplaceLimit("hexagon-cext-limit", cl::init(0), cl::Hidden,
227 return "Hexagon constant-extender optimization"; in getPassName()
570 INITIALIZE_PASS_BEGIN(HexagonConstExtenders, "hexagon-cext-opt",
571 "Hexagon constant-extender optimization", false, false)
573 INITIALIZE_PASS_END(HexagonConstExtenders, "hexagon-cext-opt",
574 "Hexagon constant-extender optimization", false, false)
801 case Hexagon::S4_storeirbt_io: in isStoreImmediate()
802 case Hexagon::S4_storeirbf_io: in isStoreImmediate()
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H A DHexagonGenPredicate.cpp92 return "Hexagon generate predicate operations"; in getPassName()
131 INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
132 "Hexagon generate predicate operations", false, false)
134 INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred", in INITIALIZE_PASS_DEPENDENCY()
135 "Hexagon generate predicate operations", false, false) in INITIALIZE_PASS_DEPENDENCY()
141 return RC == &Hexagon::PredRegsRegClass; in INITIALIZE_PASS_DEPENDENCY()
145 using namespace Hexagon; in getPredForm()
198 case Hexagon::C2_cmpeqi: in isConvertibleToPredForm()
199 case Hexagon::C4_cmpneqi: in isConvertibleToPredForm()
212 case Hexagon::C2_tfrpr: in collectPredicateGPR()
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H A DHexagonDepArch.td11 def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V…
13 …ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V…
15 …ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V…
17 …ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V…
19 …ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V…
21 …ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V…
23 …ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V…
25 …ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V68", "Enable Hexagon V…
27 …ArchV69: SubtargetFeature<"v69", "HexagonArchVersion", "Hexagon::ArchEnum::V69", "Enable Hexagon V…
29 …ArchV71: SubtargetFeature<"v71", "HexagonArchVersion", "Hexagon::ArchEnum::V71", "Enable Hexagon V…
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H A DHexagonDepArch.h16 namespace Hexagon {
33 inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) { in getCpu()
34 return StringSwitch<std::optional<Hexagon::ArchEnum>>(CPU) in getCpu()
35 .Case("generic", Hexagon::ArchEnum::V5) in getCpu()
36 .Case("hexagonv5", Hexagon::ArchEnum::V5) in getCpu()
37 .Case("hexagonv55", Hexagon::ArchEnum::V55) in getCpu()
38 .Case("hexagonv60", Hexagon::ArchEnum::V60) in getCpu()
39 .Case("hexagonv62", Hexagon::ArchEnum::V62) in getCpu()
40 .Case("hexagonv65", Hexagon::ArchEnum::V65) in getCpu()
41 .Case("hexagonv66", Hexagon::ArchEnum::V66) in getCpu()
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H A DHexagonSubtarget.h1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
71 Hexagon::ArchEnum HexagonArchVersion;
72 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
148 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5; in hasV5Ops()
151 return getHexagonArchVersion() == Hexagon::ArchEnum::V5; in hasV5OpsOnly()
154 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55; in hasV55Ops()
157 return getHexagonArchVersion() == Hexagon::ArchEnum::V55; in hasV55OpsOnly()
160 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60; in hasV60Ops()
163 return getHexagonArchVersion() == Hexagon::ArchEnum::V60; in hasV60OpsOnly()
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H A DHexagonVectorPrint.cpp37 #define DEBUG_TYPE "hexagon-vector-print"
64 StringRef getPassName() const override { return "Hexagon VectorPrint pass"; } in getPassName()
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
86 return S[R-Hexagon::V0]; in getStringReg()
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
90 return S[R-Hexagon::Q0]; in getStringReg()
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H A DHexagonFrameLowering.cpp65 #define DEBUG_TYPE "hexagon-pei"
67 // Hexagon stack frame layout as defined by the ABI:
151 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
152 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
174 EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden,
187 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
190 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
239 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
240 "Hexagon call frame information", false, false)
251 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) in getMax32BitSubRegister()
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H A DHexagonConstPropagation.cpp1829 // Hexagon-specific code.
1897 return "Hexagon Constant Propagation"; in getPassName()
1914 INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",
1915 "Hexagon Constant Propagation", false, false)
1953 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1954 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
1979 case Hexagon::A2_tfrsi: in evaluate()
1980 case Hexagon::A2_tfrpi: in evaluate()
1981 case Hexagon::CONST32: in evaluate()
1982 case Hexagon in evaluate()
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H A DHexagonGenMemAbsolute.cpp26 #define DEBUG_TYPE "hexagon-abs"
54 return "Hexagon Generate Load/Store Set Absolute Address Instruction"; in getPassName()
73 INITIALIZE_PASS(HexagonGenMemAbsolute, "hexagon-gen-load-absolute",
74 "Hexagon Generate Load/Store Set Absolute Address Instruction",
97 if (Opc != Hexagon::CONST32 && Opc != Hexagon::A2_tfrsi) in runOnMachineFunction()
221 case Hexagon::L2_loadrb_io: in isValidIndexedLoad()
222 NewOpc = Hexagon::L4_loadrb_ap; in isValidIndexedLoad()
224 case Hexagon::L2_loadrh_io: in isValidIndexedLoad()
225 NewOpc = Hexagon::L4_loadrh_ap; in isValidIndexedLoad()
227 case Hexagon::L2_loadri_io: in isValidIndexedLoad()
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H A DHexagonFrameLowering.h1 //==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
12 #include "Hexagon.h"
97 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
98 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, in getCalleeSavedSpillSlots()
99 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
100 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 }, in getCalleeSavedSpillSlots()
101 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, in getCalleeSavedSpillSlots()
102 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } in getCalleeSavedSpillSlots()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
33 #define DEBUG_TYPE "hexagon-disassembler"
36 using namespace Hexagon;
42 /// Hexagon disassembler for all Hexagon platforms.
182 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
212 case Hexagon::S2_allocframe: in remapInstruction()
213 if (MI.getOperand(0).getReg() == Hexagon::R29) { in remapInstruction()
214 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
219 case Hexagon in remapInstruction()
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaHexagon.cpp1 //===------ SemaHexagon.cpp ------ Hexagon target-specific routines -------===//
9 // This file implements semantic analysis functions specific to Hexagon.
38 { Hexagon::BI__builtin_circ_ldd, {{ 3, true, 4, 3 }} }, in CheckHexagonBuiltinArgument()
39 { Hexagon::BI__builtin_circ_ldw, {{ 3, true, 4, 2 }} }, in CheckHexagonBuiltinArgument()
40 { Hexagon::BI__builtin_circ_ldh, {{ 3, true, 4, 1 }} }, in CheckHexagonBuiltinArgument()
41 { Hexagon::BI__builtin_circ_lduh, {{ 3, true, 4, 1 }} }, in CheckHexagonBuiltinArgument()
42 { Hexagon::BI__builtin_circ_ldb, {{ 3, true, 4, 0 }} }, in CheckHexagonBuiltinArgument()
43 { Hexagon::BI__builtin_circ_ldub, {{ 3, true, 4, 0 }} }, in CheckHexagonBuiltinArgument()
44 { Hexagon::BI__builtin_circ_std, {{ 3, true, 4, 3 }} }, in CheckHexagonBuiltinArgument()
45 { Hexagon::BI__builtin_circ_stw, {{ 3, true, 4, 2 }} }, in CheckHexagonBuiltinArgument()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp30 using namespace Hexagon;
32 #define DEBUG_TYPE "hexagon-mcduplex-info"
200 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
217 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
237 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
238 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
248 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
258 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
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H A DHexagonMCInstrInfo.cpp1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
36 return Register != Hexagon::NoRegister; in isPredicated()
39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator()
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator()
50 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() { in operator ++()
71 MCInst const &Hexagon::PacketIterator::operator*() const { in operator *()
77 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const { in operator ==()
102 iterator_range<Hexagon
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H A DHexagonMCTargetDesc.cpp1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
9 // This file provides Hexagon specific target descriptions.
61 cl::desc("Disable looking for compound instructions for Hexagon"));
65 cl::desc("Disable looking for duplex instructions for Hexagon"));
68 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
70 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
72 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
74 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
76 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
78 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
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H A DHexagonMCCompound.cpp1 //=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===//
26 using namespace Hexagon;
28 #define DEBUG_TYPE "hexagon-mccompound"
92 case Hexagon::C2_cmpeq: in getCompoundCandidateGroup()
93 case Hexagon::C2_cmpgt: in getCompoundCandidateGroup()
94 case Hexagon::C2_cmpgtu: in getCompoundCandidateGroup()
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
105 case Hexagon::C2_cmpeqi: in getCompoundCandidateGroup()
106 case Hexagon::C2_cmpgti: in getCompoundCandidateGroup()
107 case Hexagon::C2_cmpgtui: in getCompoundCandidateGroup()
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H A DHexagonMCChecker.cpp10 // packet constraint rules of the Hexagon ISA.
37 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
41 ReadOnly.insert(Hexagon::PC); in init()
42 ReadOnly.insert(Hexagon::C9_8); in init()
46 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
47 Defs[Hexagon::LC0].insert(Unconditional); in init()
50 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
51 Defs[Hexagon::LC1].insert(Unconditional); in init()
94 unsigned PredReg = Hexagon::NoRegister; in init()
106 STI.hasFeature(Hexagon::ArchV69); in init()
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H A DHexagonMCELFStreamer.cpp1 //=== HexagonMCELFStreamer.cpp - Hexagon subclass of MCELFStreamer -------===//
68 assert(MCB.getOpcode() == Hexagon::BUNDLE); in emitInstruction()
154 case Hexagon::ArchV5: in featureToArchVersion()
156 case Hexagon::ArchV55: in featureToArchVersion()
158 case Hexagon::ArchV60: in featureToArchVersion()
159 case Hexagon::ExtensionHVXV60: in featureToArchVersion()
161 case Hexagon::ArchV62: in featureToArchVersion()
162 case Hexagon::ExtensionHVXV62: in featureToArchVersion()
164 case Hexagon::ArchV65: in featureToArchVersion()
165 case Hexagon::ExtensionHVXV65: in featureToArchVersion()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
83 static cl::opt<bool> AddBuildAttributes("hexagon-add-build-attributes");
163 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser()
194 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
367 return getReg() == Hexagon::SGP1_0; in issgp10Const()
525 if (getSTI().hasFeature(Hexagon::FeatureMemNoShuf)) in matchBundleOptions()
713 /// ParseDirective parses the Hexagon specific directives
745 // end of the section. Only legacy hexagon-gcc created assembly code in ParseDirectiveSubsection()
787 // Hexagon's .lcomm:
871 if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum)) in RegisterMatchesArch()
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