Lines Matching full:hexagon
37 #define DEBUG_TYPE "hexagon-vector-print"
64 StringRef getPassName() const override { return "Hexagon VectorPrint pass"; } in getPassName()
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
86 return S[R-Hexagon::V0]; in getStringReg()
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
90 return S[R-Hexagon::Q0]; in getStringReg()
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
187 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
193 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
204 INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print",
205 "Hexagon VectorPrint pass", false, false)