Lines Matching full:hexagon
10 // packet constraint rules of the Hexagon ISA.
37 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
41 ReadOnly.insert(Hexagon::PC); in init()
42 ReadOnly.insert(Hexagon::C9_8); in init()
46 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
47 Defs[Hexagon::LC0].insert(Unconditional); in init()
50 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
51 Defs[Hexagon::LC1].insert(Unconditional); in init()
94 unsigned PredReg = Hexagon::NoRegister; in init()
106 STI.hasFeature(Hexagon::ArchV69); in init()
110 if (Hexagon::R31 != R && MCID.isCall()) in init()
114 if (Hexagon::PC == R) in init()
119 if (Hexagon::USR_OVF == R) in init()
136 unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister; in init()
140 if (R == Hexagon::C8) in init()
141 R = Hexagon::USR; in init()
163 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
241 case Hexagon::SA1_addi: in isDuplexAGroup()
242 case Hexagon::SA1_addrx: in isDuplexAGroup()
243 case Hexagon::SA1_addsp: in isDuplexAGroup()
244 case Hexagon::SA1_and1: in isDuplexAGroup()
245 case Hexagon::SA1_clrf: in isDuplexAGroup()
246 case Hexagon::SA1_clrfnew: in isDuplexAGroup()
247 case Hexagon::SA1_clrt: in isDuplexAGroup()
248 case Hexagon::SA1_clrtnew: in isDuplexAGroup()
249 case Hexagon::SA1_cmpeqi: in isDuplexAGroup()
250 case Hexagon::SA1_combine0i: in isDuplexAGroup()
251 case Hexagon::SA1_combine1i: in isDuplexAGroup()
252 case Hexagon::SA1_combine2i: in isDuplexAGroup()
253 case Hexagon::SA1_combine3i: in isDuplexAGroup()
254 case Hexagon::SA1_combinerz: in isDuplexAGroup()
255 case Hexagon::SA1_combinezr: in isDuplexAGroup()
256 case Hexagon::SA1_dec: in isDuplexAGroup()
257 case Hexagon::SA1_inc: in isDuplexAGroup()
258 case Hexagon::SA1_seti: in isDuplexAGroup()
259 case Hexagon::SA1_setin1: in isDuplexAGroup()
260 case Hexagon::SA1_sxtb: in isDuplexAGroup()
261 case Hexagon::SA1_sxth: in isDuplexAGroup()
262 case Hexagon::SA1_tfr: in isDuplexAGroup()
263 case Hexagon::SA1_zxtb: in isDuplexAGroup()
264 case Hexagon::SA1_zxth: in isDuplexAGroup()
390 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { in checkPredicates()
453 if (ProducerPredInfo.Register != Hexagon::NoRegister && in checkNewValues()
477 Hexagon::DoubleRegsRegClassID) { in checkNewValues()
573 (ProducerPredicate.Register == Hexagon::NoRegister || in registerProducer()
581 if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I)) in registerProducer()
623 unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:. in checkRegisters()
624 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
636 unsigned UsrR = Hexagon::USR; in checkRegisters()
637 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
712 if (!STI.hasFeature(Hexagon::ArchV69)) { in checkValidTmpDst()
741 case Hexagon::R15: in compoundRegisterMap()
742 Register = Hexagon::R23; in compoundRegisterMap()
744 case Hexagon::R14: in compoundRegisterMap()
745 Register = Hexagon::R22; in compoundRegisterMap()
747 case Hexagon::R13: in compoundRegisterMap()
748 Register = Hexagon::R21; in compoundRegisterMap()
750 case Hexagon::R12: in compoundRegisterMap()
751 Register = Hexagon::R20; in compoundRegisterMap()
753 case Hexagon::R11: in compoundRegisterMap()
754 Register = Hexagon::R19; in compoundRegisterMap()
756 case Hexagon::R10: in compoundRegisterMap()
757 Register = Hexagon::R18; in compoundRegisterMap()
759 case Hexagon::R9: in compoundRegisterMap()
760 Register = Hexagon::R17; in compoundRegisterMap()
762 case Hexagon::R8: in compoundRegisterMap()
763 Register = Hexagon::R16; in compoundRegisterMap()
802 const bool IsPermitted = STI.hasFeature(Hexagon::ArchV67); in checkLegalVecRegPair()