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/linux/Documentation/devicetree/bindings/clock/
H A Dgoogle,gs101-clock.yaml4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
7 title: Google GS101 SoC clock controller
13 Google GS101 clock controller is comprised of several CMU units, generating
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
32 - google,gs101-cmu-misc
33 - google,gs101-cmu-hsi0
34 - google,gs101-cmu-hsi2
35 - google,gs101-cmu-peric0
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101.dtsi3 * GS101 SoC
9 #include <dt-bindings/clock/google,gs101.h>
15 compatible = "google,gs101";
279 compatible = "google,gs101-cmu-misc";
288 compatible = "google,gs101-mct",
308 compatible = "google,gs101-wdt";
320 compatible = "google,gs101-wdt";
355 compatible = "google,gs101-cmu-peric0";
365 compatible = "google,gs101-peric0-sysreg", "syscon";
371 compatible = "google,gs101-pinctrl";
[all …]
H A Dgs101-oriole.dts13 #include "gs101-pinctrl.h"
14 #include "gs101.dtsi"
18 compatible = "google,gs101-oriole", "google,gs101";
H A Dgs101-pinctrl.h3 * Pinctrl binding constants for GS101
21 /* GS101 drive strengths */
H A DMakefile4 gs101-oriole.dtb \
/linux/Documentation/devicetree/bindings/arm/
H A Dgoogle.yaml16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
22 - SoC ID ("gs101")
30 e.g. gs101 and gs101-oriole.
40 - google,gs101-oriole
41 - const: google,gs101
/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dsamsung,exynos-sysreg.yaml17 - google,gs101-apm-sysreg
18 - google,gs101-hsi2-sysreg
19 - google,gs101-peric0-sysreg
20 - google,gs101-peric1-sysreg
76 - google,gs101-hsi2-sysreg
77 - google,gs101-peric0-sysreg
78 - google,gs101-peric1-sysreg
H A Dexynos-pmu.yaml18 - google,gs101-pmu
39 - google,gs101-pmu
H A Dexynos-usi.yaml28 - google,gs101-usi
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsamsung-wdt.yaml21 - google,gs101-wdt # for Google gs101
52 or Google gs101).
58 Exynos5420, Exynos7, Exynos850 and gs101).
74 - google,gs101-wdt
88 - google,gs101-wdt
/linux/Documentation/devicetree/bindings/serial/
H A Dsamsung_uart.yaml24 - google,gs101-uart
162 - google,gs101-uart
193 #include <dt-bindings/clock/google,gs101.h>
198 compatible = "google,gs101-uart";
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c940 /* pin banks of gs101 pin-controller (ALIVE) */
952 /* pin banks of gs101 pin-controller (FAR_ALIVE) */
960 /* pin banks of gs101 pin-controller (GSACORE) */
967 /* pin banks of gs101 pin-controller (GSACTRL) */
972 /* pin banks of gs101 pin-controller (PERIC0) */
996 /* pin banks of gs101 pin-controller (PERIC1) */
1008 /* pin banks of gs101 pin-controller (HSI1) */
1014 /* pin banks of gs101 pin-controller (HSI2) */
1023 /* pin banks of gs101 pin-controller (ALIVE) */
1030 /* pin banks of gs101 pin-controller (FAR_ALIVE) */
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dsamsung,exynos-ufs.yaml18 - google,gs101-ufs
89 const: google,gs101-ufs
/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,usb3-drd-phy.yaml28 - google,gs101-usb31drd-phy
110 const: google,gs101-usb31drd-phy
/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml29 - google,gs101-mct
131 - google,gs101-mct
/linux/drivers/clk/samsung/
H A DMakefile25 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
H A Dclk-gs101.c6 * Common Clock Framework support for GS101.
14 #include <dt-bindings/clock/google,gs101.h>
1452 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
3443 CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc",
4397 .compatible = "google,gs101-cmu-apm",
4400 .compatible = "google,gs101-cmu-hsi0",
4403 .compatible = "google,gs101-cmu-hsi2",
4406 .compatible = "google,gs101-cmu-peric0",
4409 .compatible = "google,gs101-cmu-peric1",
4417 .name = "gs101-cmu",
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsamsung,pinctrl-wakeup-interrupt.yaml48 - google,gs101-wakeup-eint
/linux/drivers/soc/samsung/
H A Dexynos-pmu.c48 * Note: This SMC interface is known to be implemented on gs101 and derivative
232 .compatible = "google,gs101-pmu",
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-exynos5.yaml36 - google,gs101-hsi2c
/linux/Documentation/devicetree/bindings/spi/
H A Dsamsung,spi.yaml20 - google,gs101-spi
/linux/drivers/tty/serial/
H A Dsamsung_tty.c2503 .name = "Google GS101 UART",
2624 .name = "gs101-uart",
2647 { .compatible = "google,gs101-uart",
2820 /* gs101 always expects MMIO32 register accesses. */ in gs101_early_console_setup()
2826 OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup);
/linux/include/dt-bindings/clock/
H A Dgoogle,gs101.h6 * Device Tree binding constants for Google gs101 clock controller.
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c150 * while on versions with (like gs101), bits 2 and 3 are for the 3.0 phy (SS)
194 /* Exynos9 - GS101 */
1652 .compatible = "google,gs101-usb31drd-phy",
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h660 /* For Tensor GS101 */

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