xref: /linux/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung's Exynos USI (Universal Serial Interface)
8
9maintainers:
10  - Sam Protsenko <semen.protsenko@linaro.org>
11  - Krzysztof Kozlowski <krzk@kernel.org>
12
13description: |
14  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15  USI shares almost all internal circuits within each protocol, so only one
16  protocol can be chosen at a time. USI is modeled as a node with zero or more
17  child nodes, each representing a serial sub-node device. The mode setting
18  selects which particular function will be used.
19
20properties:
21  $nodename:
22    pattern: "^usi@[0-9a-f]+$"
23
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - google,gs101-usi
29              - samsung,exynosautov9-usi
30              - samsung,exynosautov920-usi
31          - const: samsung,exynos850-usi
32      - enum:
33          - samsung,exynos850-usi
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    maxItems: 2
40
41  clock-names:
42    items:
43      - const: pclk
44      - const: ipclk
45
46  ranges: true
47
48  "#address-cells":
49    const: 1
50
51  "#size-cells":
52    const: 1
53
54  samsung,sysreg:
55    $ref: /schemas/types.yaml#/definitions/phandle-array
56    items:
57      - items:
58          - description: phandle to System Register syscon node
59          - description: offset of SW_CONF register for this USI controller
60    description:
61      Should be phandle/offset pair. The phandle to System Register syscon node
62      (for the same domain where this USI controller resides) and the offset
63      of SW_CONF register for this USI controller.
64
65  samsung,mode:
66    $ref: /schemas/types.yaml#/definitions/uint32
67    description:
68      Selects USI function (which serial protocol to use). Refer to
69      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
70
71  samsung,clkreq-on:
72    type: boolean
73    description:
74      Enable this property if underlying protocol requires the clock to be
75      continuously provided without automatic gating. As suggested by SoC
76      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
77      multi-master mode. Usually this property is needed if USI mode is set
78      to "UART".
79
80      This property is optional.
81
82patternProperties:
83  "^i2c@[0-9a-f]+$":
84    $ref: /schemas/i2c/i2c-exynos5.yaml
85    description: Child node describing underlying I2C
86
87  "^serial@[0-9a-f]+$":
88    $ref: /schemas/serial/samsung_uart.yaml
89    description: Child node describing underlying UART/serial
90
91  "^spi@[0-9a-f]+$":
92    $ref: /schemas/spi/samsung,spi.yaml
93    description: Child node describing underlying SPI
94
95required:
96  - compatible
97  - ranges
98  - "#address-cells"
99  - "#size-cells"
100  - samsung,sysreg
101  - samsung,mode
102
103if:
104  properties:
105    compatible:
106      contains:
107        enum:
108          - samsung,exynos850-usi
109
110then:
111  properties:
112    reg:
113      maxItems: 1
114
115    clocks:
116      items:
117        - description: Bus (APB) clock
118        - description: Operating clock for UART/SPI/I2C protocol
119
120    clock-names:
121      maxItems: 2
122
123  required:
124    - reg
125    - clocks
126    - clock-names
127
128else:
129  properties:
130    reg: false
131    clocks: false
132    clock-names: false
133    samsung,clkreq-on: false
134
135additionalProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140    #include <dt-bindings/soc/samsung,exynos-usi.h>
141
142    usi0: usi@138200c0 {
143        compatible = "samsung,exynos850-usi";
144        reg = <0x138200c0 0x20>;
145        samsung,sysreg = <&sysreg_peri 0x1010>;
146        samsung,mode = <USI_V2_UART>;
147        samsung,clkreq-on; /* needed for UART mode */
148        #address-cells = <1>;
149        #size-cells = <1>;
150        ranges;
151        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
152        clock-names = "pclk", "ipclk";
153
154        serial_0: serial@13820000 {
155            compatible = "samsung,exynos850-uart";
156            reg = <0x13820000 0xc0>;
157            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
158            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
159            clock-names = "uart", "clk_uart_baud0";
160            status = "disabled";
161        };
162
163        hsi2c_0: i2c@13820000 {
164            compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
165            reg = <0x13820000 0xc0>;
166            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
167            #address-cells = <1>;
168            #size-cells = <0>;
169            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
170            clock-names = "hsi2c", "hsi2c_pclk";
171            status = "disabled";
172        };
173    };
174