Home
last modified time | relevance | path

Searched +full:gpio +full:- +full:range (Results 1 – 25 of 961) sorted by relevance

12345678910>>...39

/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
[all …]
H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range { label
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
[all …]
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range { label
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
/linux/drivers/pinctrl/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
7 * Based on bits of regulator core, gpio core and clk core
27 #include <linux/gpio.h>
28 #include <linux/gpio/driver.h>
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
[all …]
H A Dpinmux.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
7 * Based on bits of regulator core, gpio core and clk core
23 #include <linux/radix-tree.h>
37 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
43 !ops->get_functions_count || in pinmux_check_ops()
44 !ops->get_function_name || in pinmux_check_ops()
45 !ops->get_function_groups || in pinmux_check_ops()
46 !ops->set_mux) { in pinmux_check_ops()
[all …]
H A Dpinctrl-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/gpio/driver.h>
29 #include "pinctrl-at91.h"
38 * struct at91_gpio_chip: at91 gpio chip
39 * @chip: gpio chip
40 * @range: gpio range
49 * @id: gpio chip identifier
53 struct pinctrl_gpio_range range; member
114 * struct at91_pmx_func - describes AT91 pinmux functions
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 range of pin control registers can vary from one to many for each controller
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad7606.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
22 - adi,ad7605-4
23 - adi,ad7606-4
[all …]
/linux/Documentation/driver-api/
H A Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
30 be sparse - i.e. there may be gaps in the space with numbers where no
60 .. code-block:: c
[all …]
/linux/include/linux/pinctrl/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
7 * Based on bits of regulator core, gpio core and clk core
20 * struct pinmux_ops - pinmux operations, to be implemented by pin controller
44 * @gpio_request_enable: requests and enables GPIO on a certain pin.
45 * Implement this only if you can mux every pin individually as GPIO. The
46 * affected GPIO range is passed along with an offset(pin number) into that
47 * specific GPIO range - function selectors and pin groups are orthogonal
49 * @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
[all …]
H A Dpinctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
30 * struct pingroup - provides information on pingroup
50 * struct pinctrl_pin_desc - boards/machines provide information on their
54 * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
67 * struct pinctrl_gpio_range - each pin controller can provide subranges of
68 * the GPIO number space to be handled by the controller
70 * @name: a name for the chip in this range
71 * @id: an ID number for the chip in this range
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/gpio/driver.h>
28 #include <linux/pinctrl/pinconf-generic.h>
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
68 container_of(chip, struct stm32_gpio_bank, range)
73 "gpio", "af0", "af1",
93 struct pinctrl_gpio_range range; member
124 static inline int stm32_gpio_pin(int gpio) in stm32_gpio_pin() argument
126 return gpio % STM32_GPIO_PINS_PER_BANK; in stm32_gpio_pin()
[all …]
/linux/drivers/gpio/
H A Dgpio-tangier.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Tangier GPIO functions
15 #include <linux/gpio/driver.h>
35 * struct tng_wake_regs - Platform specific wake registers
47 * struct tng_gpio_pinrange - Map pin numbers to gpio numbers
48 * @gpio_base: Starting GPIO number of this range
49 * @pin_base: Starting pin number of this range
50 * @npins: Number of pins in this range
62 .npins = (gend) - (gstart) + 1, \
66 * struct tng_gpio_pin_info - Platform specific pinout information
[all …]
H A Dgpio-tangier.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Tangier GPIO driver
22 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/gpio/driver.h>
30 #include "gpio-tangier.h"
46 * struct tng_gpio_context - Context to be saved during suspend-resume
69 return priv->reg_base + reg + reg_offset * 4; in gpio_reg()
80 return priv->reg_base + reg + reg_offset * 4; in gpio_reg_and_bit()
101 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_set()
115 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_direction_input()
[all …]
/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,am62-usb";
14 clock-names = "ref";
15 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
27 interrupt-names = "host", "peripheral";
28 maximum-speed = "high-speed";
[all …]
/linux/arch/arm/mach-s3c/
H A Dgpio-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
11 /* This file contains the necessary definitions to get the basic gpio
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
31 * struct samsung_gpio_cfg GPIO configuration
33 * @get_pull: Read the current pull configuration for the GPIO
34 * @set_pull: Set the current pull configuration for the GPIO
35 * @set_config: Set the current configuration for the GPIO
36 * @get_config: Read the current configuration for the GPIO
[all …]
/linux/include/linux/gpio/
H A Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
48 * struct gpio_irq_chip - GPIO interrupt controller
54 * GPIO IRQ chip implementation, provided by GPIO driver.
61 * Interrupt translation domain; responsible for mapping between GPIO
78 * If non-NULL, will be set as the parent of this GPIO interrupt
90 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
98 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
99 * @need_valid_mask to make these GPIO lines unavailable for
113 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
[all …]
/linux/drivers/iio/adc/
H A Dad7606.h1 /* SPDX-License-Identifier: GPL-2.0 */
42 * struct ad7606_chip_info - chip specific information
62 * struct ad7606_state - driver instance specific data
66 * @range voltage range selection, selects which scale to apply
78 * @gpio_convst GPIO descriptor for conversion start signal (CONVST)
79 * @gpio_reset GPIO descriptor for device hard-reset
80 * @gpio_range GPIO descriptor for range selection
81 * @gpio_standby GPIO descriptor for stand-by signal (STBY),
82 * controls power-down mode of device
83 * @gpio_frstdata GPIO descriptor for reading from device when data
[all …]

12345678910>>...39