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Searched +full:glymur +full:- +full:gcc (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,glymur-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on Glymur SoC
10 - Taniya Das <taniya.das@oss.qualcomm.com>
14 domains on Glymur SoC.
16 See also: include/dt-bindings/clock/qcom,glymur-gcc.h
20 const: qcom,glymur-gcc
24 - description: Board XO source
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H A Dqcom,glymur-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on GLYMUR
10 - Taniya Das <taniya.das@oss.qualcomm.com>
14 power domains for the MDSS instances on GLYMUR SoC.
17 include/dt-bindings/clock/qcom,dispcc-glymur.h
22 - qcom,glymur-dispcc
26 - description: Board CXO clock
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H A Dqcom,rpmhcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,glymur-rpmh-clk
21 - qcom,milos-rpmh-clk
22 - qcom,qcs615-rpmh-clk
23 - qcom,qdu1000-rpmh-clk
24 - qcom,sa8775p-rpmh-clk
25 - qcom,sar2130p-rpmh-clk
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/linux/drivers/clk/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "GLYMUR Display Clock Controller"
28 Technologies, Inc. GLYMUR devices.
33 tristate "GLYMUR Global Clock Controller"
37 Support for the global clock controller on GLYMUR devices.
42 tristate "GLYMUR TCSR Clock Controller"
46 Support for the TCSR clock controller on GLYMUR devices.
242 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 the output clocks to the networking hardware and GCC blocks.
1411 Say Y if you want to toggle LPASS-adjacent resets within
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H A Dgcc-glymur.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/qcom,glymur-gcc.h>
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-pll.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-regmap-mux.h"
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