Lines Matching +full:glymur +full:- +full:gcc
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
19 const: qcom,snps-dwc3
21 - compatible
26 - enum:
27 - qcom,glymur-dwc3
28 - qcom,glymur-dwc3-mp
29 - qcom,ipq4019-dwc3
30 - qcom,ipq5018-dwc3
31 - qcom,ipq5332-dwc3
32 - qcom,ipq5424-dwc3
33 - qcom,ipq6018-dwc3
34 - qcom,ipq8064-dwc3
35 - qcom,ipq8074-dwc3
36 - qcom,ipq9574-dwc3
37 - qcom,kaanapali-dwc3
38 - qcom,milos-dwc3
39 - qcom,msm8953-dwc3
40 - qcom,msm8994-dwc3
41 - qcom,msm8996-dwc3
42 - qcom,msm8998-dwc3
43 - qcom,qcm2290-dwc3
44 - qcom,qcs404-dwc3
45 - qcom,qcs615-dwc3
46 - qcom,qcs8300-dwc3
47 - qcom,qdu1000-dwc3
48 - qcom,sa8775p-dwc3
49 - qcom,sar2130p-dwc3
50 - qcom,sc7180-dwc3
51 - qcom,sc7280-dwc3
52 - qcom,sc8180x-dwc3
53 - qcom,sc8180x-dwc3-mp
54 - qcom,sc8280xp-dwc3
55 - qcom,sc8280xp-dwc3-mp
56 - qcom,sdm660-dwc3
57 - qcom,sdm670-dwc3
58 - qcom,sdm845-dwc3
59 - qcom,sdx55-dwc3
60 - qcom,sdx65-dwc3
61 - qcom,sdx75-dwc3
62 - qcom,sm4250-dwc3
63 - qcom,sm6115-dwc3
64 - qcom,sm6125-dwc3
65 - qcom,sm6350-dwc3
66 - qcom,sm6375-dwc3
67 - qcom,sm8150-dwc3
68 - qcom,sm8250-dwc3
69 - qcom,sm8350-dwc3
70 - qcom,sm8450-dwc3
71 - qcom,sm8550-dwc3
72 - qcom,sm8650-dwc3
73 - qcom,sm8750-dwc3
74 - qcom,x1e80100-dwc3
75 - qcom,x1e80100-dwc3-mp
76 - const: qcom,snps-dwc3
81 power-domains:
84 required-opps:
90 - cfg_noc:: System Config NOC clock.
91 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
93 - iface:: System bus AXI clock.
94 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
96 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
101 clock-names:
105 dma-coherent: true
116 interconnect-names:
118 - const: usb-ddr
119 - const: apps-usb
124 - dwc_usb3: Core DWC3 interrupt
125 - pwr_event: Used for wakeup based on other power events.
126 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
130 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
135 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
137 only on SoCs with non-QUSB2 targets with
139 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
143 interrupt-names:
147 qcom,select-utmi-as-pipe-clk:
154 wakeup-source: true
159 - compatible
160 - reg
161 - clocks
162 - clock-names
163 - interrupts
164 - interrupt-names
167 - $ref: snps,dwc3-common.yaml#
168 - if:
173 - qcom,ipq4019-dwc3
174 - qcom,ipq5332-dwc3
179 clock-names:
181 - const: core
182 - const: sleep
183 - const: mock_utmi
185 - if:
190 - qcom,ipq8064-dwc3
195 - description: Master/Core clock, has to be >= 125 MHz
197 clock-names:
199 - const: core
201 - if:
206 - qcom,ipq9574-dwc3
207 - qcom,kaanapali-dwc3
208 - qcom,msm8953-dwc3
209 - qcom,msm8996-dwc3
210 - qcom,msm8998-dwc3
211 - qcom,qcs8300-dwc3
212 - qcom,sa8775p-dwc3
213 - qcom,sc7180-dwc3
214 - qcom,sc7280-dwc3
215 - qcom,sdm670-dwc3
216 - qcom,sdm845-dwc3
217 - qcom,sdx55-dwc3
218 - qcom,sdx65-dwc3
219 - qcom,sdx75-dwc3
220 - qcom,sm6350-dwc3
221 - qcom,sm8750-dwc3
226 clock-names:
228 - const: cfg_noc
229 - const: core
230 - const: iface
231 - const: sleep
232 - const: mock_utmi
234 - if:
239 - qcom,ipq6018-dwc3
245 clock-names:
247 - items:
248 - const: core
249 - const: sleep
250 - const: mock_utmi
251 - items:
252 - const: cfg_noc
253 - const: core
254 - const: sleep
255 - const: mock_utmi
257 - if:
262 - qcom,ipq8074-dwc3
263 - qcom,qdu1000-dwc3
268 clock-names:
270 - const: cfg_noc
271 - const: core
272 - const: sleep
273 - const: mock_utmi
275 - if:
280 - qcom,ipq5018-dwc3
281 - qcom,msm8994-dwc3
282 - qcom,qcs404-dwc3
287 clock-names:
289 - const: core
290 - const: iface
291 - const: sleep
292 - const: mock_utmi
294 - if:
299 - qcom,sc8280xp-dwc3
300 - qcom,sc8280xp-dwc3-mp
301 - qcom,x1e80100-dwc3
302 - qcom,x1e80100-dwc3-mp
307 clock-names:
309 - const: cfg_noc
310 - const: core
311 - const: iface
312 - const: sleep
313 - const: mock_utmi
314 - const: noc_aggr
315 - const: noc_aggr_north
316 - const: noc_aggr_south
317 - const: noc_sys
319 - if:
324 - qcom,sdm660-dwc3
330 clock-names:
332 - items:
333 - const: cfg_noc
334 - const: core
335 - const: iface
336 - const: sleep
337 - const: mock_utmi
338 - items:
339 - const: cfg_noc
340 - const: core
341 - const: sleep
342 - const: mock_utmi
344 - if:
349 - qcom,milos-dwc3
350 - qcom,qcm2290-dwc3
351 - qcom,qcs615-dwc3
352 - qcom,sar2130p-dwc3
353 - qcom,sc8180x-dwc3
354 - qcom,sc8180x-dwc3-mp
355 - qcom,sm6115-dwc3
356 - qcom,sm6125-dwc3
357 - qcom,sm8150-dwc3
358 - qcom,sm8250-dwc3
359 - qcom,sm8450-dwc3
360 - qcom,sm8550-dwc3
361 - qcom,sm8650-dwc3
366 clock-names:
368 - const: cfg_noc
369 - const: core
370 - const: iface
371 - const: sleep
372 - const: mock_utmi
373 - const: xo
375 - if:
380 - qcom,sm8350-dwc3
386 clock-names:
389 - const: cfg_noc
390 - const: core
391 - const: iface
392 - const: sleep
393 - const: mock_utmi
394 - const: xo
396 - if:
401 - qcom,glymur-dwc3
402 - qcom,glymur-dwc3-mp
408 clock-names:
410 - const: cfg_noc
411 - const: core
412 - const: iface
413 - const: sleep
414 - const: mock_utmi
415 - const: noc_aggr_north
416 - const: noc_aggr_south
418 - if:
423 - qcom,ipq5018-dwc3
424 - qcom,ipq6018-dwc3
425 - qcom,ipq8074-dwc3
426 - qcom,msm8953-dwc3
427 - qcom,msm8998-dwc3
433 interrupt-names:
436 - const: dwc_usb3
437 - const: pwr_event
438 - const: qusb2_phy
439 - const: ss_phy_irq
441 - if:
446 - qcom,msm8996-dwc3
447 - qcom,qcs404-dwc3
448 - qcom,sdm660-dwc3
449 - qcom,sm6115-dwc3
450 - qcom,sm6125-dwc3
456 interrupt-names:
459 - const: dwc_usb3
460 - const: pwr_event
461 - const: qusb2_phy
462 - const: hs_phy_irq
463 - const: ss_phy_irq
465 - if:
470 - qcom,ipq5332-dwc3
475 interrupt-names:
477 - const: dwc_usb3
478 - const: pwr_event
479 - const: dp_hs_phy_irq
480 - const: dm_hs_phy_irq
482 - if:
487 - qcom,glymur-dwc3
488 - qcom,milos-dwc3
489 - qcom,x1e80100-dwc3
495 interrupt-names:
498 - const: dwc_usb3
499 - const: pwr_event
500 - const: dp_hs_phy_irq
501 - const: dm_hs_phy_irq
502 - const: ss_phy_irq
504 - if:
509 - qcom,ipq4019-dwc3
510 - qcom,ipq8064-dwc3
511 - qcom,kaanapali-dwc3
512 - qcom,msm8994-dwc3
513 - qcom,qcs615-dwc3
514 - qcom,qcs8300-dwc3
515 - qcom,qdu1000-dwc3
516 - qcom,sa8775p-dwc3
517 - qcom,sc7180-dwc3
518 - qcom,sc7280-dwc3
519 - qcom,sc8180x-dwc3
520 - qcom,sc8280xp-dwc3
521 - qcom,sdm670-dwc3
522 - qcom,sdm845-dwc3
523 - qcom,sdx55-dwc3
524 - qcom,sdx65-dwc3
525 - qcom,sdx75-dwc3
526 - qcom,sm4250-dwc3
527 - qcom,sm6350-dwc3
528 - qcom,sm8150-dwc3
529 - qcom,sm8250-dwc3
530 - qcom,sm8350-dwc3
531 - qcom,sm8450-dwc3
532 - qcom,sm8550-dwc3
533 - qcom,sm8650-dwc3
534 - qcom,sm8750-dwc3
540 interrupt-names:
543 - const: dwc_usb3
544 - const: pwr_event
545 - const: hs_phy_irq
546 - const: dp_hs_phy_irq
547 - const: dm_hs_phy_irq
548 - const: ss_phy_irq
550 - if:
555 - qcom,glymur-dwc3-mp
556 - qcom,sc8180x-dwc3-mp
557 - qcom,x1e80100-dwc3-mp
563 interrupt-names:
565 - const: dwc_usb3
566 - const: pwr_event_1
567 - const: pwr_event_2
568 - const: hs_phy_1
569 - const: hs_phy_2
570 - const: dp_hs_phy_1
571 - const: dm_hs_phy_1
572 - const: dp_hs_phy_2
573 - const: dm_hs_phy_2
574 - const: ss_phy_1
575 - const: ss_phy_2
577 - if:
582 - qcom,sc8280xp-dwc3-mp
588 interrupt-names:
590 - const: dwc_usb3
591 - const: pwr_event_1
592 - const: pwr_event_2
593 - const: pwr_event_3
594 - const: pwr_event_4
595 - const: hs_phy_1
596 - const: hs_phy_2
597 - const: hs_phy_3
598 - const: hs_phy_4
599 - const: dp_hs_phy_1
600 - const: dm_hs_phy_1
601 - const: dp_hs_phy_2
602 - const: dm_hs_phy_2
603 - const: dp_hs_phy_3
604 - const: dm_hs_phy_3
605 - const: dp_hs_phy_4
606 - const: dm_hs_phy_4
607 - const: ss_phy_1
608 - const: ss_phy_2
613 - |
614 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
615 #include <dt-bindings/interrupt-controller/arm-gic.h>
616 #include <dt-bindings/interrupt-controller/irq.h>
618 #address-cells = <2>;
619 #size-cells = <2>;
622 compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3";
625 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
626 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
627 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
628 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
629 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
630 clock-names = "cfg_noc",
636 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
637 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
638 assigned-clock-rates = <19200000>, <150000000>;
646 interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq",
649 power-domains = <&gcc USB30_PRIM_GDSC>;
651 resets = <&gcc GCC_USB30_PRIM_BCR>;
657 phy-names = "usb2-phy", "usb3-phy";