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/linux/Documentation/ABI/testing/
H A Dsysfs-platform-intel-pmc6 The file exposes "Extended Test Mode Register 3" global
7 reset bits. The bits are used during an Intel platform
8 manufacturing process to indicate that consequent reset
9 of the platform is a "global reset". This type of reset
13 Display global reset setting bits for PMC.
15 * bit 31 - global reset is locked
16 * bit 20 - global reset is set
19 a platform "global reset" upon consequent platform reset,
21 The "global reset bit" should be locked on a production
22 system and the file is in read-only mode.
/linux/Documentation/devicetree/bindings/reset/
H A Dqcom,pdc-global.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PDC Global
10 - Sibi Sankar <quic_sibis@quicinc.com>
13 The bindings describes the reset-controller found on PDC-Global (Power Domain
19 - description: on SC7180 SoCs the following compatibles must be specified
21 - const: qcom,sc7180-pdc-global
22 - const: qcom,sdm845-pdc-global
[all …]
H A Dintel,rcu-gw.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
10 - Dilip Kota <eswara.kota@linux.intel.com>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
19 description: Reset controller registers.
22 intel,global-reset:
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/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dguts.txt1 * Global Utilities Block
3 The global utilities block controls power management, I/O device
4 enabling, power-on-reset configuration monitoring, general-purpose
10 - compatible : Should define the compatible device type for
11 global-utilities.
13 "fsl,qoriq-device-config-1.0"
14 "fsl,qoriq-device-config-2.0"
15 "fsl,<chip>-device-config"
16 "fsl,<chip>-guts"
17 - reg : Offset and length of the register set for the device.
[all …]
/linux/drivers/phy/st/
H A Dphy-stih407-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/reset.h>
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
65 return reset_control_deassert(phy_dev->rstport); in stih407_usb2_init_port()
73 * Only port reset is asserted, phy global reset is kept untouched in stih407_usb2_exit_port()
74 * as other ports may still be active. When all ports are in reset in stih407_usb2_exit_port()
77 * reset (like here) or global reset should be equivalent. in stih407_usb2_exit_port()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dst,stih407-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stih407-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
19 const: st,stih407-usb2-phy
23 $ref: /schemas/types.yaml#/definitions/phandle-array
25 - items:
26 - description: phandle to syscfg
27 - description: phyparam register offset
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset_types.h1 /* SPDX-License-Identifier: MIT */
15 * flags: Control various stages of the GPU reset
17 * #I915_RESET_BACKOFF - When we start a global reset, we need to
19 * any global resources that may be clobber by the reset (such as
22 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
23 * acquire the struct_mutex to reset an engine, we need an explicit
24 * flag to prevent two concurrent reset attempts in the same engine.
28 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
31 * aborted (with -EIO reported to userspace) if set.
33 * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Common Properties
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Common bindings for Qualcomm global clock control module providing the
18 '#clock-cells':
21 '#reset-cells':
24 '#power-domain-cells':
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H A Dqcom,gcc-msm8916.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-msm8916.h
19 include/dt-bindings/clock/qcom,gcc-msm8939.h
[all …]
H A Dqcom,gcc-msm8660.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8660
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module provides the clocks and resets on
18 include/dt-bindings/clock/qcom,gcc-msm8660.h
19 include/dt-bindings/reset/qcom,gcc-msm8660.h
[all …]
H A Dqcom,gcc-ipq6018.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ6018
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
12 - Robert Marko <robimarko@gmail.com>
15 Qualcomm global clock control module provides the clocks, resets and power
19 include/dt-bindings/clock/qcom,gcc-ipq6018.h
[all …]
H A Dqcom,gcc-msm8974.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
11 - Stephen Boyd <sboyd@kernel.org>
12 - Taniya Das <quic_tdas@quicinc.com>
15 Qualcomm global clock control module provides the clocks, resets and power
19 include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
20 include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
[all …]
H A Dqcom,ipq9574-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
[all …]
H A Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
13 Qualcomm global clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
[all …]
H A Dqcom,gcc-mdm9607.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-mdm9607.h
21 - $ref: qcom,gcc.yaml#
[all …]
H A Dqcom,gcc-mdm9615.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-mdm9615.h
21 - $ref: qcom,gcc.yaml#
[all …]
H A Dqcom,gcc-ipq8064.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ8064
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 Qualcomm global clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
18 include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
21 - $ref: qcom,gcc.yaml#
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H A Dqcom,gcc-apq8084.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on APQ8084
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-apq8084.h
19 include/dt-bindings/reset/qcom,gcc-apq8084.h
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx93-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX93 System Reset Controller
10 - Peng Fan <peng.fan@nxp.com>
13 The System Reset Controller (SRC) is responsible for the generation of
14 all the system reset signals and boot argument latching.
17 - Deals with all global system reset sources from other modules,
18 and generates global system reset.
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/linux/arch/x86/include/uapi/asm/
H A Ddebugreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 debug registers. Registers 0-3 contain the addresses we wish to trap on */
28 #define DR_STEP (0x4000) /* single-step */
33 bits - each field corresponds to one of the four debug registers,
51 that the processor will reset the bit after a task switch and the other
52 is global meaning that we have to explicitly reset the bit. With linux,
57 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
59 #define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
63 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
76 #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dselftest_guc_hangcheck.c1 // SPDX-License-Identifier: MIT
38 struct i915_gpu_error *global = &gt->i915->gpu_error; in intel_hang_guc() local
47 ctx = kernel_context(gt->i915, NULL); in intel_hang_guc()
53 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_hang_guc()
62 reset_count = i915_reset_count(global); in intel_hang_guc()
64 old_beat = engine->props.heartbeat_interval_ms; in intel_hang_guc()
71 ret = igt_spinner_init(&spin, engine->gt); in intel_hang_guc()
95 gt_err(gt, "Failed to reset GuC: %pe\n", ERR_PTR(ret)); in intel_hang_guc()
99 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS); in intel_hang_guc()
102 gt_err(gt, "Failed to reset GuC: status = 0x%08X\n", guc_status); in intel_hang_guc()
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/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
19 - items:
[all …]
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_fw.c1 // SPDX-License-Identifier: GPL-2.0 or MIT
9 #include <linux/dma-mapping.h>
12 #include <linux/iosys-map.h>
37 * struct panthor_fw_binary_hdr - Firmware binary header.
65 * enum panthor_fw_binary_entry_type - Firmware binary entry type
68 /** @CSF_FW_BINARY_ENTRY_TYPE_IFACE: Host <-> FW interface. */
74 /** @CSF_FW_BINARY_ENTRY_TYPE_FUTF_TEST: Unit-tests. */
117 * struct panthor_fw_binary_section_entry_hdr - Describes a section of FW binary
150 * struct panthor_fw_binary_iter - Firmware binary iterator
166 * struct panthor_fw_section - FW section
[all …]
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
6 Read/Write PMU global general storage register value,
8 Global general storage register that can be used
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
32 Read/Write PMU persistent global general storage register
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/linux/sound/mips/
H A Dhal2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
19 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
40 /* 9=Global DMA Control */
53 /* If IAR_TYPE_M=Global DMA Control: */
99 #define H2I_DMA_END 0x9108 /* global dma endian select */
107 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
120 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
136 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
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