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Searched +full:gamma +full:- +full:lut (Results 1 – 25 of 28) sorted by relevance

12

/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_aal.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
40 * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure
57 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable()
64 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable()
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
91 if (aal->data && aal->data->has_gamma) in mtk_aal_gamma_get_lut_size()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c31 (ipp_dce->regs->reg)
35 ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
38 ipp_dce->base.ctx
53 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
56 CURSOR_X_POSITION, position->x, in dce_ipp_cursor_set_position()
57 CURSOR_Y_POSITION, position->y); in dce_ipp_cursor_set_position()
60 CURSOR_HOT_SPOT_X, position->x_hotspot, in dce_ipp_cursor_set_position()
61 CURSOR_HOT_SPOT_Y, position->y_hotspot); in dce_ipp_cursor_set_position()
78 switch (attributes->color_format) { in dce_ipp_cursor_set_attributes()
98 CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, in dce_ipp_cursor_set_attributes()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
149 dpp->base.ctx, in program_gamut_remap()
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid()
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_atomic_enable()
68 hwdev->hw->modeset(hwdev, &vm); in malidp_crtc_atomic_enable()
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/linux/include/uapi/linux/media/raspberrypi/
H A Dpisp_be_config.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
5 * Copyright (C) 2021 - Raspberry Pi Ltd
98 * struct pisp_be_global_config - PiSP global enable bitmaps
112 * struct pisp_be_input_buffer_config - PiSP Back End input buffer
121 * struct pisp_be_dpc_config - PiS
337 __s8 lut[PISP_BE_CAC_LUT_SIZE][PISP_BE_CAC_LUT_SIZE][2][2]; global() member
387 __u32 lut[PISP_BE_TONEMAP_LUT_SIZE]; global() member
573 __u32 lut[PISP_BE_GAMMA_LUT_SIZE]; global() member
818 struct pisp_be_gamma_config gamma; global() member
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/linux/drivers/gpu/drm/ast/
H A Dast_mode.c3 * Parts based on xf86-video-ast
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
54 #define AST_PRIMARY_PLANE_MAX_OFFSET (BIT(16) - 1)
63 struct drm_device *dev = &ast->base; in ast_fb_vram_size()
68 cursor_offset = ast->vram_size; // no cursor; it's all ours in ast_fb_vram_size()
71 return cursor_offset - offset; in ast_fb_vram_size()
77 struct drm_device *dev = crtc->dev; in ast_set_gamma_lut()
100 struct drm_crtc *crtc = &ast->crtc; in ast_crtc_fill_gamma()
102 switch (format->format) { in ast_crtc_fill_gamma()
104 /* gamma table is used as color palette */ in ast_crtc_fill_gamma()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
118 // for example, 1080p -> 8K is 4.0, or 4000 raw value
126 // for example, 8K -> 1080p is 0.25, or 250 raw value
138 * DOC: color-management-caps
143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
153 * @gamma2_2: standard gamma
155 * @hlg: hybrid log–gamma transfer function
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp.c42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 DPP_CLOCK_ENABLE, &s->is_enabled); in dpp20_read_state()
59 // Degamma LUT (RAM) in dpp20_read_state()
61 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); in dpp20_read_state()
63 // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) in dpp20_read_state()
65 CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); in dpp20_read_state()
67 CM_3DLUT_CONFIG_STATUS, &s->lut3d_mode, in dpp20_read_state()
68 CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); in dpp20_read_state()
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H A Ddcn20_dpp_cm.c37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
143 /* Setting de gamma bypass for now */ in dpp2_set_degamma()
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A Domap_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
51 /* -----------------------------------------------------------------------------
58 return &omap_crtc->vm; in omap_crtc_timings()
64 return omap_crtc->channel; in omap_crtc_channel()
73 spin_lock_irqsave(&crtc->dev->event_lock, flags); in omap_crtc_is_pending()
74 pending = omap_crtc->pending; in omap_crtc_is_pending()
75 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in omap_crtc_is_pending()
88 return wait_event_timeout(omap_crtc->pending_wait, in omap_crtc_wait_pending()
93 /* -----------------------------------------------------------------------------
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/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
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H A Ddcn3_cm_drm_current.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Created with Inkscape (http://www.inkscape.org/) -->
11 inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
13 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
30 inkscape:window-width="1920"
31 inkscape:window-height="1011"
32 inkscape:window-x="0"
33 inkscape:window-y="0"
34 inkscape:window-maximized="1"
35 inkscape:current-layer="g2025" />
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H A Ddcn2_cm_drm_current.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Created with Inkscape (http://www.inkscape.org/) -->
11 inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
13 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
30 inkscape:window-width="1920"
31 inkscape:window-height="1011"
32 inkscape:window-x="0"
33 inkscape:window-y="0"
34 inkscape:window-maximized="1"
35 inkscape:current-layer="g2025" />
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 DPP_CLOCK_ENABLE, &s->is_enabled); in dpp30_read_state()
52 // Pre-degamma (ROM) in dpp30_read_state()
54 PRE_DEGAM_MODE, &s->pre_dgam_mode, in dpp30_read_state()
55 PRE_DEGAM_SELECT, &s->pre_dgam_select); in dpp30_read_state()
57 // Gamma Correction (RAM) in dpp30_read_state()
59 CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode); in dpp30_read_state()
60 if (s->gamcor_mode) { in dpp30_read_state()
[all …]
H A Ddcn30_dpp_cm.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
66 if (state_mode == 2) {//Programmable RAM LUT in dpp30_get_gamcor_current()
85 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg; in dpp3_program_gammcor_lut()
86 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg; in dpp3_program_gammcor_lut()
87 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg; in dpp3_program_gammcor_lut()
89 /*fill in the LUT with all base values to be used by pwl module in dpp3_program_gammcor_lut()
90 * HW auto increments the LUT index: back-to-back write in dpp3_program_gammcor_lut()
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/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-only
19 wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); in wl1251_boot_target_enable_interrupts()
40 /* 1.2 check pWhalBus->uSelfClearTime if the in wl1251_boot_soft_reset()
43 return -1; in wl1251_boot_soft_reset()
70 static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { in wl1251_boot_init_seq() local
118 * PG 1.2: set the clock request time to be ref_clk_settling_time - in wl1251_boot_init_seq()
122 tmp = init_data - 0x21; in wl1251_boot_init_seq()
143 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; in wl1251_boot_init_seq()
146 /* set fractional divider according to Appendix C-BB PLL in wl1251_boot_init_seq()
149 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; in wl1251_boot_init_seq()
[all …]
/linux/include/drm/
H A Ddrm_mode_config.h42 * struct drm_mode_config_funcs - basic driver provided mode setting functions
44 * Some global (i.e. not per-CRTC, connector, etc) mode setting functions that
59 * ie. when (@mode_cmd->flags & DRM_MODE_FB_MODIFIERS) == 0.
70 * driver-specific information (like the internal native buffer object
120 * - Checking that the modes, framebuffers, scaling and placement
123 * - Checking that any hidden shared resources are not oversubscribed.
128 * - Checking that virtualized resources exported to userspace are not
131 * example is dual-pipe operations (which generally should be hidden
138 * - Check that any transitional state is possible and that if
142 * - Check any other constraints the driver or hardware might have.
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_crtc.c1 // SPDX-License-Identifier: MIT
43 struct drm_crtc *crtc = &acrtc->base; in amdgpu_dm_crtc_handle_vblank()
44 struct drm_device *dev = crtc->dev; in amdgpu_dm_crtc_handle_vblank()
49 spin_lock_irqsave(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
51 /* Send completion event for cursor-only commits */ in amdgpu_dm_crtc_handle_vblank()
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in amdgpu_dm_crtc_handle_vblank()
53 drm_crtc_send_vblank_event(crtc, acrtc->event); in amdgpu_dm_crtc_handle_vblank()
55 acrtc->event = NULL; in amdgpu_dm_crtc_handle_vblank()
58 spin_unlock_irqrestore(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); in amdgpu_dm_crtc_modeset_required()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
40 * - graphic color keyer
41 * - graphic cursor compositing
42 * - graphic or video image source to destination scaling
43 * - image sharping
44 * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4
45 * - Color Space Conversion
46 * - Host LUT gamma adjustment
47 * - Color Gamut Remap
48 * - brightness and contrast adjustment.
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndw.c33 #include <linux/iosys-map.h>
51 nvif_object_dtor(&ctxdma->object); in nv50_wndw_ctxdma_del()
52 list_del(&ctxdma->head); in nv50_wndw_ctxdma_del()
59 struct nouveau_drm *drm = nouveau_drm(fb->dev); in nv50_wndw_ctxdma_new()
78 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { in nv50_wndw_ctxdma_new()
79 if (ctxdma->object.handle == handle) in nv50_wndw_ctxdma_new()
84 return ERR_PTR(-ENOMEM); in nv50_wndw_ctxdma_new()
85 list_add(&ctxdma->head, &wndw->ctxdma.list); in nv50_wndw_ctxdma_new()
90 args.base.limit = drm->client.device.info.ram_user - 1; in nv50_wndw_ctxdma_new()
92 if (drm->client.device.info.chipset < 0x80) { in nv50_wndw_ctxdma_new()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_regamma_v.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
71 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
88 value = dm_read_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
97 dm_write_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
111 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); in configure_regamma_mode()
139 params->arr_points[0].custom_float_x, in regamma_config_regions_and_segments()
149 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, in regamma_config_regions_and_segments()
156 params->arr_points[0].custom_float_slope, in regamma_config_regions_and_segments()
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Andy Yan <andy.yan@rock-chips.com>
12 #include <linux/media-bus-format.h>
44 +----------+ +-------------+ +-----------+
47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
48 +----------+ +-------------+ |N from 6 layers| | |
49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
52 +----------+ +-------------+ +-----------+
54 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #include <soc/bcm2835/raspberrypi-firmware.h>
206 struct drm_device *drm = &hvs->vc4->base; in vc4_hvs_dump_state()
207 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); in vc4_hvs_dump_state()
213 drm_print_regset32(&p, &hvs->regset); in vc4_hvs_dump_state()
219 readl((u32 __iomem *)hvs->dlist + i + 0), in vc4_hvs_dump_state()
220 readl((u32 __iomem *)hvs->dlist + i + 1), in vc4_hvs_dump_state()
221 readl((u32 __iomem *)hvs->dlist + i + 2), in vc4_hvs_dump_state()
222 readl((u32 __iomem *)hvs->dlist + i + 3)); in vc4_hvs_dump_state()
230 struct drm_debugfs_entry *entry = m->private; in vc4_hvs_debugfs_underrun()
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit CRTCs
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
35 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_read()
37 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); in rcar_du_crtc_read()
42 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_write()
44 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); in rcar_du_crtc_write()
49 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_clr()
51 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_clr()
52 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr()
[all …]
/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include "include/uapi/intel-ipu3.h"
106 #define IMGU_REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
121 /* For each definition there is signal pair : valid [bit 0]- accept [bit 1] */
151 #define IMGU_GP_STRMON_STAT_MOD_PORT_S2V(n) (1 << (((n) - 1) * 2 + 20))
154 #define IMGU_GP_STRMON_STAT_ACCS_PORT_ACC(n) (1 << (((n) - 1) * 2))
157 #define IMGU_GP_STRMON_STAT_ACCS2SP1_MON_PORT_ACC(n) (1 << (((n) - 1) * 2))
160 #define IMGU_GP_STRMON_STAT_ACCS2SP2_MON_PORT_ACC(n) (1 << (((n) - 1) * 2))
212 #define IMGU_GDC_LUT_MASK ((1 << 12) - 1) /* Range -1024..+1024 */
353 /* n = 0..IPU3_CSS_PIPE_ID_NUM-1 */
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