xref: /linux/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dce_ipp.h"
27 #include "reg_helper.h"
28 #include "dm_services.h"
29 
30 #define REG(reg) \
31 	(ipp_dce->regs->reg)
32 
33 #undef FN
34 #define FN(reg_name, field_name) \
35 	ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
36 
37 #define CTX \
38 	ipp_dce->base.ctx
39 
40 
dce_ipp_cursor_set_position(struct input_pixel_processor * ipp,const struct dc_cursor_position * position,const struct dc_cursor_mi_param * param)41 static void dce_ipp_cursor_set_position(
42 	struct input_pixel_processor *ipp,
43 	const struct dc_cursor_position *position,
44 	const struct dc_cursor_mi_param *param)
45 {
46 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
47 
48 	/* lock cursor registers */
49 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
50 
51 	/* Flag passed in structure differentiates cursor enable/disable. */
52 	/* Update if it differs from cached state. */
53 	REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
54 
55 	REG_SET_2(CUR_POSITION, 0,
56 		CURSOR_X_POSITION, position->x,
57 		CURSOR_Y_POSITION, position->y);
58 
59 	REG_SET_2(CUR_HOT_SPOT, 0,
60 		CURSOR_HOT_SPOT_X, position->x_hotspot,
61 		CURSOR_HOT_SPOT_Y, position->y_hotspot);
62 
63 	/* unlock cursor registers */
64 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
65 }
66 
dce_ipp_cursor_set_attributes(struct input_pixel_processor * ipp,const struct dc_cursor_attributes * attributes)67 static void dce_ipp_cursor_set_attributes(
68 	struct input_pixel_processor *ipp,
69 	const struct dc_cursor_attributes *attributes)
70 {
71 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
72 	int mode;
73 
74 	/* Lock cursor registers */
75 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
76 
77 	/* Program cursor control */
78 	switch (attributes->color_format) {
79 	case CURSOR_MODE_MONO:
80 		mode = 0;
81 		break;
82 	case CURSOR_MODE_COLOR_1BIT_AND:
83 		mode = 1;
84 		break;
85 	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
86 		mode = 2;
87 		break;
88 	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
89 		mode = 3;
90 		break;
91 	default:
92 		BREAK_TO_DEBUGGER(); /* unsupported */
93 		mode = 0;
94 	}
95 
96 	REG_UPDATE_3(CUR_CONTROL,
97 		CURSOR_MODE, mode,
98 		CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
99 		CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
100 
101 	if (attributes->color_format == CURSOR_MODE_MONO) {
102 		REG_SET_3(CUR_COLOR1, 0,
103 			CUR_COLOR1_BLUE, 0,
104 			CUR_COLOR1_GREEN, 0,
105 			CUR_COLOR1_RED, 0);
106 
107 		REG_SET_3(CUR_COLOR2, 0,
108 			CUR_COLOR2_BLUE, 0xff,
109 			CUR_COLOR2_GREEN, 0xff,
110 			CUR_COLOR2_RED, 0xff);
111 	}
112 
113 	/*
114 	 * Program cursor size -- NOTE: HW spec specifies that HW register
115 	 * stores size as (height - 1, width - 1)
116 	 */
117 	REG_SET_2(CUR_SIZE, 0,
118 		CURSOR_WIDTH, attributes->width-1,
119 		CURSOR_HEIGHT, attributes->height-1);
120 
121 	/* Program cursor surface address */
122 	/* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor
123 	 * surface base address in byte. It is 4K byte aligned.
124 	 * The correct way to program cursor surface address is to first write
125 	 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS
126 	 */
127 	REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,
128 		CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part);
129 
130 	REG_SET(CUR_SURFACE_ADDRESS, 0,
131 		CURSOR_SURFACE_ADDRESS, attributes->address.low_part);
132 
133 	/* Unlock Cursor registers. */
134 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
135 }
136 
137 
dce_ipp_program_prescale(struct input_pixel_processor * ipp,struct ipp_prescale_params * params)138 static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
139 				     struct ipp_prescale_params *params)
140 {
141 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
142 
143 	/* set to bypass mode first before change */
144 	REG_UPDATE(PRESCALE_GRPH_CONTROL,
145 		   GRPH_PRESCALE_BYPASS, 1);
146 
147 	REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
148 		  GRPH_PRESCALE_SCALE_R, params->scale,
149 		  GRPH_PRESCALE_BIAS_R, params->bias);
150 
151 	REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
152 		  GRPH_PRESCALE_SCALE_G, params->scale,
153 		  GRPH_PRESCALE_BIAS_G, params->bias);
154 
155 	REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
156 		  GRPH_PRESCALE_SCALE_B, params->scale,
157 		  GRPH_PRESCALE_BIAS_B, params->bias);
158 
159 	if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
160 		REG_UPDATE(PRESCALE_GRPH_CONTROL,
161 			   GRPH_PRESCALE_BYPASS, 0);
162 
163 		/* If prescale is in use, then legacy lut should be bypassed */
164 		REG_UPDATE(INPUT_GAMMA_CONTROL,
165 			   GRPH_INPUT_GAMMA_MODE, 1);
166 	}
167 }
168 
dce_ipp_program_input_lut(struct input_pixel_processor * ipp,const struct dc_gamma * gamma)169 static void dce_ipp_program_input_lut(
170 	struct input_pixel_processor *ipp,
171 	const struct dc_gamma *gamma)
172 {
173 	int i;
174 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
175 
176 	/* power on LUT memory */
177 	if (REG(DCFE_MEM_PWR_CTRL))
178 		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
179 
180 	/* enable all */
181 	REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
182 
183 	/* 256 entry mode */
184 	REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
185 
186 	/* LUT-256, unsigned, integer, new u0.12 format */
187 	REG_SET_3(DC_LUT_CONTROL, 0,
188 		DC_LUT_DATA_R_FORMAT, 3,
189 		DC_LUT_DATA_G_FORMAT, 3,
190 		DC_LUT_DATA_B_FORMAT, 3);
191 
192 	/* start from index 0 */
193 	REG_SET(DC_LUT_RW_INDEX, 0,
194 		DC_LUT_RW_INDEX, 0);
195 
196 	for (i = 0; i < gamma->num_entries; i++) {
197 		REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
198 				dc_fixpt_round(
199 					gamma->entries.red[i]));
200 		REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
201 				dc_fixpt_round(
202 					gamma->entries.green[i]));
203 		REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
204 				dc_fixpt_round(
205 					gamma->entries.blue[i]));
206 	}
207 
208 	/* power off LUT memory */
209 	if (REG(DCFE_MEM_PWR_CTRL))
210 		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
211 
212 	/* bypass prescale, enable legacy LUT */
213 	REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
214 	REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
215 }
216 
dce_ipp_set_degamma(struct input_pixel_processor * ipp,enum ipp_degamma_mode mode)217 static void dce_ipp_set_degamma(
218 	struct input_pixel_processor *ipp,
219 	enum ipp_degamma_mode mode)
220 {
221 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
222 	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
223 
224 	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
225 
226 	REG_SET_3(DEGAMMA_CONTROL, 0,
227 		  GRPH_DEGAMMA_MODE, degamma_type,
228 		  CURSOR_DEGAMMA_MODE, degamma_type,
229 		  CURSOR2_DEGAMMA_MODE, degamma_type);
230 }
231 
232 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_ipp_set_degamma(struct input_pixel_processor * ipp,enum ipp_degamma_mode mode)233 static void dce60_ipp_set_degamma(
234 	struct input_pixel_processor *ipp,
235 	enum ipp_degamma_mode mode)
236 {
237 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
238 	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
239 
240 	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
241 	/* DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL reg */
242 	REG_SET_2(DEGAMMA_CONTROL, 0,
243 		  GRPH_DEGAMMA_MODE, degamma_type,
244 		  CURSOR_DEGAMMA_MODE, degamma_type);
245 }
246 #endif
247 
248 static const struct ipp_funcs dce_ipp_funcs = {
249 	.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
250 	.ipp_cursor_set_position = dce_ipp_cursor_set_position,
251 	.ipp_program_prescale = dce_ipp_program_prescale,
252 	.ipp_program_input_lut = dce_ipp_program_input_lut,
253 	.ipp_set_degamma = dce_ipp_set_degamma
254 };
255 
256 #if defined(CONFIG_DRM_AMD_DC_SI)
257 static const struct ipp_funcs dce60_ipp_funcs = {
258 	.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
259 	.ipp_cursor_set_position = dce_ipp_cursor_set_position,
260 	.ipp_program_prescale = dce_ipp_program_prescale,
261 	.ipp_program_input_lut = dce_ipp_program_input_lut,
262 	.ipp_set_degamma = dce60_ipp_set_degamma
263 };
264 #endif
265 
266 
267 /*****************************************/
268 /* Constructor, Destructor               */
269 /*****************************************/
270 
dce_ipp_construct(struct dce_ipp * ipp_dce,struct dc_context * ctx,int inst,const struct dce_ipp_registers * regs,const struct dce_ipp_shift * ipp_shift,const struct dce_ipp_mask * ipp_mask)271 void dce_ipp_construct(
272 	struct dce_ipp *ipp_dce,
273 	struct dc_context *ctx,
274 	int inst,
275 	const struct dce_ipp_registers *regs,
276 	const struct dce_ipp_shift *ipp_shift,
277 	const struct dce_ipp_mask *ipp_mask)
278 {
279 	ipp_dce->base.ctx = ctx;
280 	ipp_dce->base.inst = inst;
281 	ipp_dce->base.funcs = &dce_ipp_funcs;
282 
283 	ipp_dce->regs = regs;
284 	ipp_dce->ipp_shift = ipp_shift;
285 	ipp_dce->ipp_mask = ipp_mask;
286 }
287 
288 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_ipp_construct(struct dce_ipp * ipp_dce,struct dc_context * ctx,int inst,const struct dce_ipp_registers * regs,const struct dce_ipp_shift * ipp_shift,const struct dce_ipp_mask * ipp_mask)289 void dce60_ipp_construct(
290 	struct dce_ipp *ipp_dce,
291 	struct dc_context *ctx,
292 	int inst,
293 	const struct dce_ipp_registers *regs,
294 	const struct dce_ipp_shift *ipp_shift,
295 	const struct dce_ipp_mask *ipp_mask)
296 {
297 	ipp_dce->base.ctx = ctx;
298 	ipp_dce->base.inst = inst;
299 	ipp_dce->base.funcs = &dce60_ipp_funcs;
300 
301 	ipp_dce->regs = regs;
302 	ipp_dce->ipp_shift = ipp_shift;
303 	ipp_dce->ipp_mask = ipp_mask;
304 }
305 #endif
306 
dce_ipp_destroy(struct input_pixel_processor ** ipp)307 void dce_ipp_destroy(struct input_pixel_processor **ipp)
308 {
309 	kfree(TO_DCE_IPP(*ipp));
310 	*ipp = NULL;
311 }
312