Lines Matching +full:gamma +full:- +full:lut
33 #include <linux/iosys-map.h>
51 nvif_object_dtor(&ctxdma->object); in nv50_wndw_ctxdma_del()
52 list_del(&ctxdma->head); in nv50_wndw_ctxdma_del()
59 struct nouveau_drm *drm = nouveau_drm(fb->dev); in nv50_wndw_ctxdma_new()
78 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { in nv50_wndw_ctxdma_new()
79 if (ctxdma->object.handle == handle) in nv50_wndw_ctxdma_new()
84 return ERR_PTR(-ENOMEM); in nv50_wndw_ctxdma_new()
85 list_add(&ctxdma->head, &wndw->ctxdma.list); in nv50_wndw_ctxdma_new()
90 args.base.limit = drm->client.device.info.ram_user - 1; in nv50_wndw_ctxdma_new()
92 if (drm->client.device.info.chipset < 0x80) { in nv50_wndw_ctxdma_new()
96 if (drm->client.device.info.chipset < 0xc0) { in nv50_wndw_ctxdma_new()
101 if (drm->client.device.info.chipset < 0xd0) { in nv50_wndw_ctxdma_new()
110 ret = nvif_object_ctor(wndw->ctxdma.parent, "kmsFbCtxDma", handle, in nv50_wndw_ctxdma_new()
111 NV_DMA_IN_MEMORY, &args, argc, &ctxdma->object); in nv50_wndw_ctxdma_new()
123 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); in nv50_wndw_wait_armed()
124 if (asyw->set.ntfy) { in nv50_wndw_wait_armed()
125 return wndw->func->ntfy_wait_begun(disp->sync, in nv50_wndw_wait_armed()
126 asyw->ntfy.offset, in nv50_wndw_wait_armed()
127 wndw->wndw.base.device); in nv50_wndw_wait_armed()
137 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
139 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
140 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
141 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
142 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
143 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
145 interlock[wndw->interlock.type] |= wndw->interlock.data; in nv50_wndw_flush_clr()
153 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; in nv50_wndw_flush_set()
154 asyw->image.interval = 1; in nv50_wndw_flush_set()
157 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); in nv50_wndw_flush_set()
158 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); in nv50_wndw_flush_set()
159 if (asyw->set.image) wndw->func->image_set(wndw, asyw); in nv50_wndw_flush_set()
161 if (asyw->set.xlut ) { in nv50_wndw_flush_set()
162 if (asyw->ilut) { in nv50_wndw_flush_set()
163 asyw->xlut.i.offset = in nv50_wndw_flush_set()
164 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer, in nv50_wndw_flush_set()
165 asyw->ilut, asyw->xlut.i.load); in nv50_wndw_flush_set()
167 wndw->func->xlut_set(wndw, asyw); in nv50_wndw_flush_set()
170 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); in nv50_wndw_flush_set()
171 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); in nv50_wndw_flush_set()
172 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); in nv50_wndw_flush_set()
173 if (asyw->set.point) { in nv50_wndw_flush_set()
174 if (asyw->set.point = false, asyw->set.mask) in nv50_wndw_flush_set()
175 interlock[wndw->interlock.type] |= wndw->interlock.data; in nv50_wndw_flush_set()
176 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; in nv50_wndw_flush_set()
178 wndw->immd->point(wndw, asyw); in nv50_wndw_flush_set()
179 wndw->immd->update(wndw, interlock); in nv50_wndw_flush_set()
181 interlock[wndw->interlock.type] |= wndw->interlock.data; in nv50_wndw_flush_set()
188 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); in nv50_wndw_ntfy_enable()
190 asyw->ntfy.handle = wndw->wndw.sync.handle; in nv50_wndw_ntfy_enable()
191 asyw->ntfy.offset = wndw->ntfy; in nv50_wndw_ntfy_enable()
192 asyw->ntfy.awaken = false; in nv50_wndw_ntfy_enable()
193 asyw->set.ntfy = true; in nv50_wndw_ntfy_enable()
195 wndw->func->ntfy_reset(disp->sync, wndw->ntfy); in nv50_wndw_ntfy_enable()
196 wndw->ntfy ^= 0x10; in nv50_wndw_ntfy_enable()
204 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); in nv50_wndw_atomic_check_release()
205 NV_ATOMIC(drm, "%s release\n", wndw->plane.name); in nv50_wndw_atomic_check_release()
206 wndw->func->release(wndw, asyw, asyh); in nv50_wndw_atomic_check_release()
207 asyw->ntfy.handle = 0; in nv50_wndw_atomic_check_release()
208 asyw->sema.handle = 0; in nv50_wndw_atomic_check_release()
209 asyw->xlut.handle = 0; in nv50_wndw_atomic_check_release()
210 memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle)); in nv50_wndw_atomic_check_release()
216 switch (asyw->state.fb->format->format) { in nv50_wndw_atomic_check_acquire_yuv()
218 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8; in nv50_wndw_atomic_check_acquire_yuv()
221 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8; in nv50_wndw_atomic_check_acquire_yuv()
225 return -EINVAL; in nv50_wndw_atomic_check_acquire_yuv()
228 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601; in nv50_wndw_atomic_check_acquire_yuv()
235 switch (asyw->state.fb->format->format) { in nv50_wndw_atomic_check_acquire_rgb()
237 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8; in nv50_wndw_atomic_check_acquire_rgb()
241 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8; in nv50_wndw_atomic_check_acquire_rgb()
244 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5; in nv50_wndw_atomic_check_acquire_rgb()
248 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5; in nv50_wndw_atomic_check_acquire_rgb()
252 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10; in nv50_wndw_atomic_check_acquire_rgb()
256 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8; in nv50_wndw_atomic_check_acquire_rgb()
260 asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10; in nv50_wndw_atomic_check_acquire_rgb()
264 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; in nv50_wndw_atomic_check_acquire_rgb()
267 return -EINVAL; in nv50_wndw_atomic_check_acquire_rgb()
270 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB; in nv50_wndw_atomic_check_acquire_rgb()
280 struct drm_framebuffer *fb = asyw->state.fb; in nv50_wndw_atomic_check_acquire()
281 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); in nv50_wndw_atomic_check_acquire()
286 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); in nv50_wndw_atomic_check_acquire()
288 if (fb != armw->state.fb || !armw->visible || modeset) { in nv50_wndw_atomic_check_acquire()
291 asyw->image.w = fb->width; in nv50_wndw_atomic_check_acquire()
292 asyw->image.h = fb->height; in nv50_wndw_atomic_check_acquire()
293 asyw->image.kind = kind; in nv50_wndw_atomic_check_acquire()
302 if (asyw->image.kind) { in nv50_wndw_atomic_check_acquire()
303 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR; in nv50_wndw_atomic_check_acquire()
304 if (drm->client.device.info.chipset >= 0xc0) in nv50_wndw_atomic_check_acquire()
305 asyw->image.blockh = tile_mode >> 4; in nv50_wndw_atomic_check_acquire()
307 asyw->image.blockh = tile_mode; in nv50_wndw_atomic_check_acquire()
308 asyw->image.blocks[0] = fb->pitches[0] / 64; in nv50_wndw_atomic_check_acquire()
309 asyw->image.pitch[0] = 0; in nv50_wndw_atomic_check_acquire()
311 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH; in nv50_wndw_atomic_check_acquire()
312 asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB; in nv50_wndw_atomic_check_acquire()
313 asyw->image.blocks[0] = 0; in nv50_wndw_atomic_check_acquire()
314 asyw->image.pitch[0] = fb->pitches[0]; in nv50_wndw_atomic_check_acquire()
317 if (!asyh->state.async_flip) in nv50_wndw_atomic_check_acquire()
318 asyw->image.interval = 1; in nv50_wndw_atomic_check_acquire()
320 asyw->image.interval = 0; in nv50_wndw_atomic_check_acquire()
322 if (asyw->image.interval) in nv50_wndw_atomic_check_acquire()
323 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; in nv50_wndw_atomic_check_acquire()
325 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE; in nv50_wndw_atomic_check_acquire()
327 asyw->set.image = wndw->func->image_set != NULL; in nv50_wndw_atomic_check_acquire()
330 if (wndw->func->scale_set) { in nv50_wndw_atomic_check_acquire()
331 asyw->scale.sx = asyw->state.src_x >> 16; in nv50_wndw_atomic_check_acquire()
332 asyw->scale.sy = asyw->state.src_y >> 16; in nv50_wndw_atomic_check_acquire()
333 asyw->scale.sw = asyw->state.src_w >> 16; in nv50_wndw_atomic_check_acquire()
334 asyw->scale.sh = asyw->state.src_h >> 16; in nv50_wndw_atomic_check_acquire()
335 asyw->scale.dw = asyw->state.crtc_w; in nv50_wndw_atomic_check_acquire()
336 asyw->scale.dh = asyw->state.crtc_h; in nv50_wndw_atomic_check_acquire()
337 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale))) in nv50_wndw_atomic_check_acquire()
338 asyw->set.scale = true; in nv50_wndw_atomic_check_acquire()
341 if (wndw->func->blend_set) { in nv50_wndw_atomic_check_acquire()
342 asyw->blend.depth = 255 - asyw->state.normalized_zpos; in nv50_wndw_atomic_check_acquire()
343 asyw->blend.k1 = asyw->state.alpha >> 8; in nv50_wndw_atomic_check_acquire()
344 switch (asyw->state.pixel_blend_mode) { in nv50_wndw_atomic_check_acquire()
346 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; in nv50_wndw_atomic_check_acquire()
347 …asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_… in nv50_wndw_atomic_check_acquire()
350 …asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIME… in nv50_wndw_atomic_check_acquire()
351 …asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_… in nv50_wndw_atomic_check_acquire()
355 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; in nv50_wndw_atomic_check_acquire()
356 … asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1; in nv50_wndw_atomic_check_acquire()
359 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) in nv50_wndw_atomic_check_acquire()
360 asyw->set.blend = true; in nv50_wndw_atomic_check_acquire()
363 if (wndw->immd) { in nv50_wndw_atomic_check_acquire()
364 asyw->point.x = asyw->state.crtc_x; in nv50_wndw_atomic_check_acquire()
365 asyw->point.y = asyw->state.crtc_y; in nv50_wndw_atomic_check_acquire()
366 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) in nv50_wndw_atomic_check_acquire()
367 asyw->set.point = true; in nv50_wndw_atomic_check_acquire()
370 return wndw->func->acquire(wndw, asyw, asyh); in nv50_wndw_atomic_check_acquire()
379 struct drm_property_blob *ilut = asyh->state.degamma_lut; in nv50_wndw_atomic_check_lut()
381 /* I8 format without an input LUT makes no sense, and the in nv50_wndw_atomic_check_lut()
382 * HW error-checks for this. in nv50_wndw_atomic_check_lut()
384 * In order to handle legacy gamma, when there's no input in nv50_wndw_atomic_check_lut()
385 * LUT we need to steal the output LUT and use it instead. in nv50_wndw_atomic_check_lut()
387 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) { in nv50_wndw_atomic_check_lut()
389 * that do a modeset before providing a gamma table. in nv50_wndw_atomic_check_lut()
393 if (!(ilut = asyh->state.gamma_lut)) { in nv50_wndw_atomic_check_lut()
394 asyw->visible = false; in nv50_wndw_atomic_check_lut()
398 if (wndw->func->ilut) in nv50_wndw_atomic_check_lut()
399 asyh->wndw.olut |= BIT(wndw->id); in nv50_wndw_atomic_check_lut()
401 asyh->wndw.olut &= ~BIT(wndw->id); in nv50_wndw_atomic_check_lut()
404 if (!ilut && wndw->func->ilut_identity && in nv50_wndw_atomic_check_lut()
405 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && in nv50_wndw_atomic_check_lut()
406 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { in nv50_wndw_atomic_check_lut()
411 /* Recalculate LUT state. */ in nv50_wndw_atomic_check_lut()
412 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); in nv50_wndw_atomic_check_lut()
413 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { in nv50_wndw_atomic_check_lut()
414 wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut)); in nv50_wndw_atomic_check_lut()
415 asyw->xlut.handle = wndw->wndw.vram.handle; in nv50_wndw_atomic_check_lut()
416 asyw->xlut.i.buffer = !asyw->xlut.i.buffer; in nv50_wndw_atomic_check_lut()
417 asyw->set.xlut = true; in nv50_wndw_atomic_check_lut()
419 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
423 if (wndw->func->olut_core && in nv50_wndw_atomic_check_lut()
424 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) in nv50_wndw_atomic_check_lut()
425 asyw->set.xlut = true; in nv50_wndw_atomic_check_lut()
427 if (wndw->func->csc && asyh->state.ctm) { in nv50_wndw_atomic_check_lut()
428 const struct drm_color_ctm *ctm = asyh->state.ctm->data; in nv50_wndw_atomic_check_lut()
429 wndw->func->csc(wndw, asyw, ctm); in nv50_wndw_atomic_check_lut()
430 asyw->csc.valid = true; in nv50_wndw_atomic_check_lut()
431 asyw->set.csc = true; in nv50_wndw_atomic_check_lut()
433 asyw->csc.valid = false; in nv50_wndw_atomic_check_lut()
434 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
437 /* Can't do an immediate flip while changing the LUT. */ in nv50_wndw_atomic_check_lut()
438 asyh->state.async_flip = false; in nv50_wndw_atomic_check_lut()
448 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv50_wndw_atomic_check()
450 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); in nv50_wndw_atomic_check()
456 NV_ATOMIC(drm, "%s atomic_check\n", plane->name); in nv50_wndw_atomic_check()
461 if (asyw->state.crtc) { in nv50_wndw_atomic_check()
462 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); in nv50_wndw_atomic_check()
465 modeset = drm_atomic_crtc_needs_modeset(&asyh->state); in nv50_wndw_atomic_check()
466 asyw->visible = asyh->state.active; in nv50_wndw_atomic_check()
468 asyw->visible = false; in nv50_wndw_atomic_check()
472 if (armw->state.crtc) { in nv50_wndw_atomic_check()
473 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); in nv50_wndw_atomic_check()
478 /* LUT configuration can potentially cause the window to be disabled. */ in nv50_wndw_atomic_check()
479 if (asyw->visible && wndw->func->xlut_set && in nv50_wndw_atomic_check()
480 (!armw->visible || in nv50_wndw_atomic_check()
481 asyh->state.color_mgmt_changed || in nv50_wndw_atomic_check()
482 asyw->state.fb->format->format != in nv50_wndw_atomic_check()
483 armw->state.fb->format->format)) { in nv50_wndw_atomic_check()
490 if (asyw->visible) { in nv50_wndw_atomic_check()
496 asyh->wndw.mask |= BIT(wndw->id); in nv50_wndw_atomic_check()
498 if (armw->visible) { in nv50_wndw_atomic_check()
500 harm->wndw.mask &= ~BIT(wndw->id); in nv50_wndw_atomic_check()
509 if (!asyw->visible || modeset) { in nv50_wndw_atomic_check()
510 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
511 asyw->clr.sema = armw->sema.handle != 0; in nv50_wndw_atomic_check()
512 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check()
513 if (asyw->clr.xlut && asyw->visible) in nv50_wndw_atomic_check()
514 asyw->set.xlut = asyw->xlut.handle != 0; in nv50_wndw_atomic_check()
515 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check()
516 if (wndw->func->image_clr) in nv50_wndw_atomic_check()
517 asyw->clr.image = armw->image.handle[0] != 0; in nv50_wndw_atomic_check()
526 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv50_wndw_cleanup_fb()
529 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); in nv50_wndw_cleanup_fb()
530 if (!old_state->fb) in nv50_wndw_cleanup_fb()
533 nvbo = nouveau_gem_object(old_state->fb->obj[0]); in nv50_wndw_cleanup_fb()
540 struct drm_framebuffer *fb = state->fb; in nv50_wndw_prepare_fb()
541 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv50_wndw_prepare_fb()
549 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb); in nv50_wndw_prepare_fb()
550 if (!asyw->state.fb) in nv50_wndw_prepare_fb()
553 nvbo = nouveau_gem_object(fb->obj[0]); in nv50_wndw_prepare_fb()
558 if (wndw->ctxdma.parent) { in nv50_wndw_prepare_fb()
559 if (wndw->wndw.base.user.oclass < GB202_DISP_WINDOW_CHANNEL_DMA) { in nv50_wndw_prepare_fb()
566 if (asyw->visible) in nv50_wndw_prepare_fb()
567 asyw->image.handle[0] = ctxdma->object.handle; in nv50_wndw_prepare_fb()
570 if (asyw->visible) { in nv50_wndw_prepare_fb()
574 asyw->image.handle[0] = NV50_DISP_HANDLE_WNDW_CTX(0); in nv50_wndw_prepare_fb()
583 asyw->image.offset[0] = nvbo->offset; in nv50_wndw_prepare_fb()
585 if (wndw->func->prepare) { in nv50_wndw_prepare_fb()
586 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); in nv50_wndw_prepare_fb()
590 wndw->func->prepare(wndw, asyh, asyw); in nv50_wndw_prepare_fb()
621 blk_off = nv50_get_block_off(x, y, sb->pitch[0]); in nv50_set_pixel_swizzle()
632 iosys_map_wr(&sb->map[0], off, u32, color); in nv50_set_pixel_swizzle()
641 blk_off = nv50_get_block_off(x, y, sb->width); in nv50_set_pixel()
647 iosys_map_wr(&sb->map[0], off, u32, color); in nv50_set_pixel()
655 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv50_wndw_get_scanout_buffer()
656 u16 chipset = drm->client.device.info.chipset; in nv50_wndw_get_scanout_buffer()
657 u8 family = drm->client.device.info.family; in nv50_wndw_get_scanout_buffer()
661 if (!plane->state || !plane->state->fb) in nv50_wndw_get_scanout_buffer()
662 return -EINVAL; in nv50_wndw_get_scanout_buffer()
664 fb = plane->state->fb; in nv50_wndw_get_scanout_buffer()
665 nvbo = nouveau_gem_object(fb->obj[0]); in nv50_wndw_get_scanout_buffer()
668 if (nvbo->comp || fb->format->num_planes != 1) in nv50_wndw_get_scanout_buffer()
669 return -EOPNOTSUPP; in nv50_wndw_get_scanout_buffer()
672 drm_warn(plane->dev, "nouveau bo map failed, panic won't be displayed\n"); in nv50_wndw_get_scanout_buffer()
673 return -ENOMEM; in nv50_wndw_get_scanout_buffer()
676 if (nvbo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK) in nv50_wndw_get_scanout_buffer()
677 iosys_map_set_vaddr_iomem(&sb->map[0], (void __iomem *)nvbo->kmap.virtual); in nv50_wndw_get_scanout_buffer()
679 iosys_map_set_vaddr(&sb->map[0], nvbo->kmap.virtual); in nv50_wndw_get_scanout_buffer()
681 sb->height = fb->height; in nv50_wndw_get_scanout_buffer()
682 sb->width = fb->width; in nv50_wndw_get_scanout_buffer()
683 sb->pitch[0] = fb->pitches[0]; in nv50_wndw_get_scanout_buffer()
684 sb->format = fb->format; in nv50_wndw_get_scanout_buffer()
691 if (fb->format->cpp[0] != 4) in nv50_wndw_get_scanout_buffer()
692 return -EOPNOTSUPP; in nv50_wndw_get_scanout_buffer()
697 sb->set_pixel = nv50_set_pixel_swizzle; in nv50_wndw_get_scanout_buffer()
699 sb->set_pixel = nv50_set_pixel; in nv50_wndw_get_scanout_buffer()
724 __drm_atomic_helper_plane_destroy_state(&asyw->state); in nv50_wndw_atomic_destroy_state()
731 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); in nv50_wndw_atomic_duplicate_state()
735 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); in nv50_wndw_atomic_duplicate_state()
736 asyw->sema = armw->sema; in nv50_wndw_atomic_duplicate_state()
737 asyw->ntfy = armw->ntfy; in nv50_wndw_atomic_duplicate_state()
738 asyw->ilut = NULL; in nv50_wndw_atomic_duplicate_state()
739 asyw->xlut = armw->xlut; in nv50_wndw_atomic_duplicate_state()
740 asyw->csc = armw->csc; in nv50_wndw_atomic_duplicate_state()
741 asyw->image = armw->image; in nv50_wndw_atomic_duplicate_state()
742 asyw->point = armw->point; in nv50_wndw_atomic_duplicate_state()
743 asyw->clr.mask = 0; in nv50_wndw_atomic_duplicate_state()
744 asyw->set.mask = 0; in nv50_wndw_atomic_duplicate_state()
745 return &asyw->state; in nv50_wndw_atomic_duplicate_state()
751 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : in nv50_wndw_zpos_default()
752 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; in nv50_wndw_zpos_default()
763 if (plane->state) in nv50_wndw_reset()
764 plane->funcs->atomic_destroy_state(plane, plane->state); in nv50_wndw_reset()
766 __drm_atomic_helper_plane_reset(plane, &asyw->state); in nv50_wndw_reset()
775 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) { in nv50_wndw_destroy()
779 nv50_dmac_destroy(&wndw->wimm); in nv50_wndw_destroy()
780 nv50_dmac_destroy(&wndw->wndw); in nv50_wndw_destroy()
782 nv50_lut_fini(&wndw->ilut); in nv50_wndw_destroy()
784 drm_plane_cleanup(&wndw->plane); in nv50_wndw_destroy()
789 * and the modifier was validated against the device-wides modifier list at FB
795 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv50_plane_format_mod_supported()
802 if (drm->client.device.info.chipset < 0xc0) { in nv50_plane_format_mod_supported()
808 for (i = 0; i < info->num_planes; i++) in nv50_plane_format_mod_supported()
809 if ((info->cpp[i] != 4) && kind != 0x70) return false; in nv50_plane_format_mod_supported()
839 struct nvif_mmu *mmu = &drm->client.mmu; in nv50_wndw_new_()
847 return -ENOMEM; in nv50_wndw_new_()
848 wndw->func = func; in nv50_wndw_new_()
849 wndw->id = index; in nv50_wndw_new_()
850 wndw->interlock.type = interlock_type; in nv50_wndw_new_()
851 wndw->interlock.data = interlock_data; in nv50_wndw_new_()
853 wndw->ctxdma.parent = &wndw->wndw.base.user; in nv50_wndw_new_()
854 INIT_LIST_HEAD(&wndw->ctxdma.list); in nv50_wndw_new_()
861 format_modifiers = nouveau_display(dev)->format_modifiers; in nv50_wndw_new_()
863 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, format, nformat, in nv50_wndw_new_()
864 format_modifiers, type, "%s-%d", name, index); in nv50_wndw_new_()
872 drm_plane_helper_add(&wndw->plane, &nv50_wndw_primary_helper); in nv50_wndw_new_()
874 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); in nv50_wndw_new_()
876 if (wndw->func->ilut) { in nv50_wndw_new_()
877 ret = nv50_lut_init(disp, mmu, &wndw->ilut); in nv50_wndw_new_()
882 if (wndw->func->blend_set) { in nv50_wndw_new_()
883 ret = drm_plane_create_zpos_property(&wndw->plane, in nv50_wndw_new_()
884 nv50_wndw_zpos_default(&wndw->plane), 0, 254); in nv50_wndw_new_()
888 ret = drm_plane_create_alpha_property(&wndw->plane); in nv50_wndw_new_()
892 ret = drm_plane_create_blend_mode_property(&wndw->plane, in nv50_wndw_new_()
899 ret = drm_plane_create_zpos_immutable_property(&wndw->plane, in nv50_wndw_new_()
900 nv50_wndw_zpos_default(&wndw->plane)); in nv50_wndw_new_()
924 struct nv50_disp *disp = nv50_disp(drm->dev); in nv50_wndw_new()
927 cid = nvif_mclass(&disp->disp->object, wndws); in nv50_wndw_new()