| /linux/drivers/acpi/acpica/ |
| H A D | utmath.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: utmath - Integer math support routines
14 /* Structures used only for 64-bit divide */
22 u64 full; member
28 * Optional support for 64-bit double-precision integer multiply and shift.
29 * This code is configurable and is implemented in order to support 32-bit
30 * kernel environments where a 64-bit double-precision math library is not
39 * PARAMETERS: multiplicand - 64-bit multiplicand
40 * multiplier - 32-bit multiplier
41 * out_product - Pointer to where the product is returned
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| /linux/drivers/comedi/drivers/ |
| H A D | jr3_pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * is 16 bits, but aligned on a 32 bit PCI boundary
31 * two-byte words.
42 * Channels 1-6 contain the coupled force data Fx through Mz. Channel
43 * 7 contains the sensor's calibration data. The use of channels 8-15
70 * the full scales.
84 * which axes to use in computing the vectors. Each bit signifies
85 * selection of a single axis. The V1x axis bit corresponds to a hex
86 * value of 0x0001 and the V2z bit corresponds to a hex value of
91 * calculated. Setting the changeV1 bit or the changeV2 bit will
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| /linux/drivers/net/ethernet/sunplus/ |
| H A D | spl2sw_define.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
12 #define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */
13 #define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */
14 #define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */
15 #define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */
16 #define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */
17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */
18 #define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */
19 #define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */
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| /linux/include/linux/ |
| H A D | cnt32_to_63.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
43 * the top bit of both counters (hardware and in memory) differ then the
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | core-imp-def.json | 93 … "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
96 … "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
99 "PublicDescription": "Macro-ops speculatively decoded",
102 "BriefDescription": "Macro-ops speculatively decoded"
117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| H A D | core-imp-def.json | 93 … "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
96 … "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
99 "PublicDescription": "Macro-ops speculatively decoded",
102 "BriefDescription": "Macro-ops speculatively decoded"
117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
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| /linux/include/asm-generic/bitops/ |
| H A D | instrumented-atomic.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file provides wrappers with sanitizer instrumentation for atomic bit
8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),
17 * set_bit - Atomically set a bit in memory
18 * @nr: the bit to set
24 * restricted to acting on a single-word quantity.
33 * clear_bit - Clears a bit in memory
34 * @nr: Bit to clear
46 * change_bit - Toggle a bit in memory
47 * @nr: Bit to change
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| /linux/drivers/gpib/include/ |
| H A D | tnt4882_registers.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 // register number for auxiliary command register when swap bit is set (9914 mode)
49 /* TURBO-488 registers bit definitions */
62 /* CFG -- Configuration Register (write only) */
65 * (tnt4882 one-chip and newer only?)
75 TNT_B_16BIT = (1 << 0), /* 1=FIFO is 16-bit register, 0=8-bit */
78 /* CMDR -- Command Register */
80 CLRSC = 0x2, /* clear the system controller bit */
81 SETSC = 0x3, /* set the system controller bit */
89 /* HSSEL -- handshake select register (write only) */
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| /linux/drivers/scsi/ |
| H A D | aha1542.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define STST BIT(7) /* Self Test in Progress */
11 #define DIAGF BIT(6) /* Internal Diagnostic Failure */
12 #define INIT BIT(5) /* Mailbox Initialization Required */
13 #define IDLE BIT(4) /* SCSI Host Adapter Idle */
14 #define CDF BIT(3) /* Command/Data Out Port Full */
15 #define DF BIT(2) /* Data In Port Full */
16 /* BIT(1) is reserved */
17 #define INVDCMD BIT(0) /* Invalid H A Command */
21 #define ANYINTR BIT(7) /* Any Interrupt */
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | tsx_async_abort.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
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| /linux/tools/perf/Documentation/ |
| H A D | perf-arm-spe.txt | 1 perf-arm-spe(1)
5 ----
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
9 --------
11 'perf record' -e arm_spe//
14 -----------
17 events down to individual instructions. Rather than being interrupt-driven, it picks an
27 5. Interrupt when the buffer is full
33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The
35 sample. This minimum interval is used by the driver if no interval is specified. A pseudo-random
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| /linux/Documentation/networking/device_drivers/can/ |
| H A D | can327.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
7 --------
14 -----------
26 -------------
29 into full fledged (as far as possible) CAN interfaces.
33 order to fake full-duplex operation.
36 enough to implement simple request-response protocols (such as OBD II),
50 -----------
59 ----------------------------------
68 --debug \
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| /linux/arch/m68k/include/asm/ |
| H A D | mcfuart.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
77 * Define bit flags in Mode Register 2 (MR2).
85 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
90 * Define bit flags in Status Register (USR).
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| /linux/arch/mips/include/asm/ |
| H A D | cmpxchg.h | 6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
20 * - Get an error at compile-time due to __compiletime_error, if supported by
25 * - Get an error at link-time due to the call to the missing function.
44 " " __SYNC(full, loongson3_war) " \n" \
122 " " __SYNC(full, loongson3_war) " \n" \
131 "2: " __SYNC(full, loongson3_war) " \n" \
223 # include <asm-generic/cmpxchg-local.h>
236 * The assembly below has to combine 32 bit values into a 64 bit in __cmpxchg64()
237 * register, and split 64 bit values from one register into two. If we in __cmpxchg64()
240 * most significant 32 bits of the 64 bit values we're using. In order in __cmpxchg64()
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| /linux/Documentation/hwmon/ |
| H A D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
33 setting a bit to 0 enables the voltage input.
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
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| /linux/sound/soc/sprd/ |
| H A D | sprd-mcdt.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
129 u32 full, u32 empty) in sprd_mcdt_dac_set_watermark() argument
135 water_mark |= full & MCDT_CH_FIFO_AF_MASK; in sprd_mcdt_dac_set_watermark()
141 u32 full, u32 empty) in sprd_mcdt_adc_set_watermark() argument
147 water_mark |= full & MCDT_CH_FIFO_AF_MASK; in sprd_mcdt_adc_set_watermark()
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
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| /linux/include/uapi/linux/ |
| H A D | mii.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
44 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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| /linux/drivers/iommu/generic_pt/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
19 The kunit tests require this to be enabled to get full coverage.
36 tristate "IOMMU page table for 64-bit AMD IOMMU v1"
41 power of 2 and decodes the full 64-bit IOVA space.
46 tristate "IOMMU page table for Intel VT-d Second Stage"
49 iommu_domain implementation for the Intel VT-d's 64 bit 3/4/5
56 tristate "IOMMU page table for x86 64-bit, 4/5 levels"
59 iommu_domain implementation for the x86 64-bit 4/5 level page table.
60 It supports 4K/2M/1G page sizes and can decode a sign-extended
61 portion of the 64-bit IOVA space.
|
| /linux/fs/nilfs2/ |
| H A D | the_nilfs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2005-2008 Nippon Telegraph and Telephone Corporation.
19 #include <linux/backing-dev.h>
36 * struct the_nilfs - struct to supervise multiple nilfs mount points
43 * @ns_sbh: buffer heads of on-disk super blocks
51 * @ns_segnum: index number of the latest full segment.
52 * @ns_nextnum: index number of the full segment index to be used next
53 * @ns_pseg_offset: offset of next partial segment in the current full segment
69 * @ns_cptree: rb-tree of all mounted checkpoints (nilfs_root)
79 * @ns_blocksize_bits: bit length of block size
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| /linux/include/linux/spi/ |
| H A D | sh_msiof.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
33 #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
34 #define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
35 #define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
37 #define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
38 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
40 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
46 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
47 #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
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| /linux/include/linux/ceph/ |
| H A D | msgr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
23 * The full banner string should have the form: "ceph v2\n<le16>"
35 #define DEFINE_MSGR2_FEATURE(bit, incarnation, name) \ argument
36 static const uint64_t __maybe_unused CEPH_MSGR2_FEATURE_##name = (1ULL << bit); \
38 (1ULL << bit | CEPH_MSGR2_INCARNATION_##incarnation);
51 * Rollover-safe type and comparator for 32-bit sequence numbers.
52 * Comparator returns -1, 0, or 1.
58 return (__s32)a - (__s32)b; in ceph_seq_cmp()
63 * entity_name -- logical name for a process participating in the
82 * entity_addr -- network address
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| /linux/fs/overlayfs/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 An overlay filesystem combines two filesystems - an 'upper' filesystem
78 directory. This full index is used to detect overlay filesystems
80 the same lower dir. The full index may incur some overhead on mount
85 That is, mounting an overlay which has a full index on a kernel
88 Most users should say N here and enable this feature on a case-by-
97 depends on 64BIT
101 inodes to a unified address space. The mapped 64bit inode numbers
102 might not be compatible with applications that expect 32bit inodes.
104 If compatibility with applications that expect 32bit inodes is not an
|
| /linux/Documentation/filesystems/ext4/ |
| H A D | checksums.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
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| /linux/sound/soc/intel/atom/sst/ |
| H A D | sst_ipc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * sst_ipc.c - Intel SST Driver for audio engine
5 * Copyright (C) 2008-14 Intel Corporation
25 #include "../sst-mfld-platform.h"
33 dev_dbg(ctx->dev, "Enter\n"); in sst_create_block()
37 msg->condition = false; in sst_create_block()
38 msg->on = true; in sst_create_block()
39 msg->msg_id = msg_id; in sst_create_block()
40 msg->drv_id = drv_id; in sst_create_block()
41 spin_lock_bh(&ctx->block_lock); in sst_create_block()
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| /linux/include/net/page_pool/ |
| H A D | types.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/dma-direction.h>
12 #define PP_FLAG_DMA_MAP BIT(0) /* Should page_pool do the DMA
15 #define PP_FLAG_DMA_SYNC_DEV BIT(1) /* If set all pages that the driver gets
17 * DMA-synced-for-device according to
20 * Please note DMA-sync-for-CPU is still
23 #define PP_FLAG_SYSTEM_POOL BIT(2) /* Global system page_pool */
32 #define PP_FLAG_ALLOW_UNREADABLE_NETMEM BIT(3)
38 #define PP_DMA_INDEX_LIMIT XA_LIMIT(1, BIT(PP_DMA_INDEX_BITS) - 1)
44 * use-case. The NAPI budget is 64 packets. After a NAPI poll the RX
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