1 // SPDX-License-Identifier: GPL-2.0
24 #define LBR_KERNEL	BIT(LBR_SELECT_KERNEL)
25 #define LBR_USER	BIT(LBR_SELECT_USER)
26 #define LBR_JCC		BIT(LBR_SELECT_JCC)
27 #define LBR_REL_CALL	BIT(LBR_SELECT_CALL_NEAR_REL)
28 #define LBR_IND_CALL	BIT(LBR_SELECT_CALL_NEAR_IND)
29 #define LBR_RETURN	BIT(LBR_SELECT_RET_NEAR)
30 #define LBR_REL_JMP	BIT(LBR_SELECT_JMP_NEAR_REL)
31 #define LBR_IND_JMP	BIT(LBR_SELECT_JMP_NEAR_IND)
32 #define LBR_FAR		BIT(LBR_SELECT_FAR_BRANCH)
33 #define LBR_NOT_SUPP	-1	/* unsupported filter */
47 		u64		full;  member
58 		u64		full;  member
92 	u32 shift = 64 - boot_cpu_data.x86_virt_bits;  in sign_ext_branch_ip()
100 	int br_sel = cpuc->br_sel, offset, type, i, j;  in amd_pmu_lbr_filter()
110 	for (i = 0; i < cpuc->lbr_stack.nr; i++) {  in amd_pmu_lbr_filter()
111 		from = cpuc->lbr_entries[i].from;  in amd_pmu_lbr_filter()
112 		to = cpuc->lbr_entries[i].to;  in amd_pmu_lbr_filter()
121 			cpuc->lbr_entries[i].from += offset;  in amd_pmu_lbr_filter()
128 			cpuc->lbr_entries[i].from = 0;	/* mark invalid */  in amd_pmu_lbr_filter()
133 			cpuc->lbr_entries[i].type = common_branch_type(type);  in amd_pmu_lbr_filter()
140 	for (i = 0; i < cpuc->lbr_stack.nr; ) {  in amd_pmu_lbr_filter()
141 		if (!cpuc->lbr_entries[i].from) {  in amd_pmu_lbr_filter()
143 			while (++j < cpuc->lbr_stack.nr)  in amd_pmu_lbr_filter()
144 				cpuc->lbr_entries[j - 1] = cpuc->lbr_entries[j];  in amd_pmu_lbr_filter()
145 			cpuc->lbr_stack.nr--;  in amd_pmu_lbr_filter()
146 			if (!cpuc->lbr_entries[i].from)  in amd_pmu_lbr_filter()
163 	struct perf_branch_entry *br = cpuc->lbr_entries;  in amd_pmu_lbr_read()
167 	if (!cpuc->lbr_users)  in amd_pmu_lbr_read()
171 		entry.from.full	= amd_pmu_lbr_get_from(i);  in amd_pmu_lbr_read()
172 		entry.to.full	= amd_pmu_lbr_get_to(i);  in amd_pmu_lbr_read()
201 		 * non-speculative but took the correct path.  in amd_pmu_lbr_read()
211 	cpuc->lbr_stack.nr = out;  in amd_pmu_lbr_read()
217 	cpuc->lbr_stack.hw_idx = 0;  in amd_pmu_lbr_read()
247 	struct hw_perf_event_extra *reg = &event->hw.branch_reg;  in amd_pmu_lbr_setup_filter()
248 	u64 br_type = event->attr.branch_sample_type;  in amd_pmu_lbr_setup_filter()
254 		return -EOPNOTSUPP;  in amd_pmu_lbr_setup_filter()
288 	reg->reg = mask;  in amd_pmu_lbr_setup_filter()
297 			return -EOPNOTSUPP;  in amd_pmu_lbr_setup_filter()
304 	reg->config = mask ^ LBR_SELECT_MASK;  in amd_pmu_lbr_setup_filter()
315 		event->attach_state |= PERF_ATTACH_SCHED_CB;  in amd_pmu_lbr_hw_config()
334 	cpuc->last_task_ctx = NULL;  in amd_pmu_lbr_reset()
335 	cpuc->last_log_id = 0;  in amd_pmu_lbr_reset()
342 	struct hw_perf_event_extra *reg = &event->hw.branch_reg;  in amd_pmu_lbr_add()
348 		cpuc->lbr_select = 1;  in amd_pmu_lbr_add()
349 		cpuc->lbr_sel->config = reg->config;  in amd_pmu_lbr_add()
350 		cpuc->br_sel = reg->reg;  in amd_pmu_lbr_add()
353 	perf_sched_cb_inc(event->pmu);  in amd_pmu_lbr_add()
355 	if (!cpuc->lbr_users++ && !event->total_time_running)  in amd_pmu_lbr_add()
367 		cpuc->lbr_select = 0;  in amd_pmu_lbr_del()
369 	cpuc->lbr_users--;  in amd_pmu_lbr_del()
370 	WARN_ON_ONCE(cpuc->lbr_users < 0);  in amd_pmu_lbr_del()
371 	perf_sched_cb_dec(event->pmu);  in amd_pmu_lbr_del()
383 	if (cpuc->lbr_users && sched_in)  in amd_pmu_lbr_sched_task()
392 	if (!cpuc->lbr_users || !x86_pmu.lbr_nr)  in amd_pmu_lbr_enable_all()
396 	if (cpuc->lbr_select) {  in amd_pmu_lbr_enable_all()
397 		lbr_select = cpuc->lbr_sel->config & LBR_SELECT_MASK;  in amd_pmu_lbr_enable_all()
414 	if (!cpuc->lbr_users || !x86_pmu.lbr_nr)  in amd_pmu_lbr_disable_all()
425 		return -EOPNOTSUPP;  in amd_pmu_lbr_init()
428 	ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);  in amd_pmu_lbr_init()
431 	pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);  in amd_pmu_lbr_init()