Home
last modified time | relevance | path

Searched +full:fsin +full:- +full:enable (Results 1 – 21 of 21) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fai
[all...]
/freebsd/usr.bin/clang/llc/
H A Dllc.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetOptions.h1 //===-- llvm/Target/TargetOptions.h - Target Options ------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
29 Default, // Target-specific (either soft or hard depending on triple, etc).
37 Fast, // Enable fusion of FP ops wherever it's profitable.
39 Strict // Never fuse FP-ops.
48 // into 4 types: pointer to non-function, struct,
79 EABI4, // Target-specific (either 4, 5 or gnu depending on triple).
88 /// individual feature-flag settings, that suit the preferences of the
[all …]
H A DTargetSelectionDAG.td1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces used by SelectionDAG
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
25 // SDTCisVT - The specified operand has exactly this VT.
32 // SDTCisInt - The specified operand has integer type.
35 // SDTCisFP - The specified operand has floating-point type.
38 // SDTCisVec - The specified operand has a vector type.
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td1 //===- TargetGlobalISel.td - Common code for GlobalISel ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces used to support
13 // This is intended as a compatibility layer, to enable reuse of target
17 //===----------------------------------------------------------------------===//
26 // SelectionDAG has separate nodes for atomic and non-atomic memory operations
43 // SelectionDAG does not differentiate between convergent and non-convergent
54 // G_INTTOPTR - SelectionDAG has no equivalent.
55 // G_PTRTOINT - SelectionDAG has no equivalent.
[all …]
/freebsd/sys/netinet/
H A Din_pcb.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 2007-2009 Robert N. M. Watson
7 * Copyright (c) 2010-2011 Juniper Networks, Inc.
8 * Copyright (c) 2021-2022 Gleb Smirnoff <glebius@FreeBSD.org>
120 VNET_DEFINE(int, ipport_lowfirstauto) = IPPORT_RESERVED - 1; /* 1023 */
132 VNET_DEFINE(int, ipport_reservedhigh) = IPPORT_RESERVED - 1; /* 1023 */
135 /* Enable random ephemeral port allocation by default. */
155 RANGECHK(V_ipport_lowfirstauto, 1, IPPORT_RESERVED - 1); in sysctl_net_ipport_check()
156 RANGECHK(V_ipport_lowlastauto, 1, IPPORT_RESERVED - 1); in sysctl_net_ipport_check()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
106 // Allocate a full-sized argument for the 64-bit ABI.
112 "Can't handle non-64 bits locations"); in Analyze_CC_Sparc64_Full()
121 // Promote integers to %i0-%i5. in Analyze_CC_Sparc64_Full()
124 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). in Analyze_CC_Sparc64_Full()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
69 #define DEBUG_TYPE "hexagon-lowering"
71 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
76 EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden,
77 cl::desc("Enable Hexagon SDNode scheduling"));
79 static cl::opt<bool> EnableFastMath("ffast-math", cl::Hidden,
80 cl::desc("Enable Fast Math processing"));
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
35 "amdgpu-bypass-slow-div",
36 cl::desc("Skip 64-bit divide for dynamic 32-bit values"),
56 // In order for this to be a signed 24-bit value, bit 23, must in numBitsSigned()
70 // Enable ganging up loads and stores in the memcpy DAG lowering. in AMDGPUTargetLowering()
181 // There are no 64-bit extloads. These should be done as a 32-bit extload and in AMDGPUTargetLowering()
182 // an extension to 64-bit. in AMDGPUTargetLowering()
[all …]
H A DSIISelLowering.cpp1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
49 #define DEBUG_TYPE "si-lower"
54 "amdgpu-disable-loop-alignment",
59 "amdgpu-use-divergent-register-indexing",
66 return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign(); in denormalModeIsFlushAllF32()
71 return Info->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign(); in denormalModeIsFlushAllF64F16()
97 const TargetRegisterClass *V64RegClass = TRI->getVGPR64Class(); in SITargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1 //===- BasicTTIImpl.h -------------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// terms of the target-independent code generator and TargetLowering
14 //===----------------------------------------------------------------------===//
96 Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, in getBroadcastShuffleOverhead()
99 for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { in getBroadcastShuffleOverhead()
100 Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, in getBroadcastShuffleOverhead()
118 for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { in getPermuteShuffleOverhead()
119 Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, in getPermuteShuffleOverhead()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
52 #define DEBUG_TYPE "mips-isel"
55 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
58 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
122 // f16 is a storage-only type, always promote it to f32. in MipsSETargetLowering()
145 setOperationAction(ISD::FSIN, MVT::f16, Promote); in MipsSETargetLowering()
225 // MIPS32r6 replaces the accumulator-based multiplies with a three register in MipsSETargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
109 #define DEBUG_TYPE "aarch64-lower"
119 "aarch64-elf-ldtls-generation", cl::Hidden,
124 EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden,
125 cl::desc("Enable AArch64 logical imm instruction "
134 EnableCombineMGatherIntrinsics("aarch64-enable-mgather-combine", cl::Hidden,
139 static cl::opt<bool> EnableExtToTBL("aarch64-enable-ext-to-tbl", cl::Hidden,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1 //=- LoongArchISelLowering.cpp - LoongArch DAG Lowering Implementation ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "loongarch-isel-lowering"
41 static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
102 // Expand bitreverse.i16 with native-width bitrev and shift for now, before in LoongArchTargetLowering()
107 // LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and in LoongArchTargetLowering()
109 // and i32 could still be byte-swapped relatively cheaply. in LoongArchTargetLowering()
178 setOperationAction(ISD::FSIN, MVT::f32, Expand); in LoongArchTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
106 #define DEBUG_TYPE "ppc-lowering"
108 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
111 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
114 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
117 static cl::opt<bool> DisableSCO("disable-ppc-sco",
120 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "ve-lower"
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
91 if (Subtarget->enableVPU()) { in initRegisterClasses()
212 // VE doesn't have instructions for fp<->uint, so expand them by llvm in initSPUActions()
225 /// Floating-point Ops { in initSPUActions()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
122 #define DEBUG_TYPE "arm-isel"
131 ARMInterworking("arm-interworking", cl::Hidden,
132 cl::desc("Enable / disable ARM interworking (for debugging only)"),
136 "arm-promote-constant", cl::Hidden,
137 cl::desc("Enable / disable promotion of unnamed_addr constants into "
141 "arm-promote-constant-max-size", cl::Hidden,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "x86-isel"
74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
78 "alignment set by x86-experimental-pref-loop-alignment."),
82 "x86-br-merging-base-cost", cl::init(2),
88 "will be merged, and above which conditionals will be split. Set to -1 "
93 "x86-br-merging-ccmp-bias", cl::init(6),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
51 #define DEBUG_TYPE "riscv-lower"
56 DEBUG_TYPE "-ext-max-web-size", cl::Hidden,
62 AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden,
68 DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden,
74 FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "systemz-lower"
47 // Chain if this is a strict floating-point comparison.
127 setStackPointerRegisterToSaveRestore(Regs->getStackPointerRegister()); in SystemZTargetLowering()
129 // TODO: It may be better to default to latency-oriented scheduling, however in SystemZTargetLowering()
130 // LLVM's current latency-oriented scheduler can't handle physreg definitions in SystemZTargetLowering()
131 // such as SystemZ has with CC, so set this to the register-pressure in SystemZTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1 //===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
87 /// makeVTList - Return an instance of the SDVTList struct initialized with the
104 static cl::opt<bool> EnableMemCpyDAGOpt("enable-memcpy-dag-opt",
108 static cl::opt<int> MaxLdStGlue("ldstmemcpy-glue-max",
113 LLVM_DEBUG(dbgs() << Msg; V.getNode()->dump(G);); in NewSDValueDbgMsg()
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
[all …]