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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
69 #define DEBUG_TYPE "hexagon-lowering"
71 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
76 EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden,
77 cl::desc("Enable Hexagon SDNode scheduling"));
79 static cl::opt<bool> EnableFastMath("ffast-math", cl::Hidden,
80 cl::desc("Enable Fast Math processing"));
82 static cl::opt<int> MinimumJumpTables("minimum-jump-tables", cl::Hidden,
87 MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::init(6),
91 MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::init(4),
95 MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::init(6),
99 MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden,
104 MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::init(8),
108 MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::init(4),
111 static cl::opt<bool> AlignLoads("hexagon-align-loads",
116 DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden,
169 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
197 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
206 // CCValAssign - represent the assignment of the return value to locations.
209 // CCState - Info about the registers and stack slot.
265 return CI->isTailCall();
344 /// LowerCallResult - Lower the result values of an ISD::CALL into the
400 /// LowerCall - Functions arguments are copied from virtual regs to
421 unsigned NumParams = CLI.CB ? CLI.CB->getFunctionType()->getNumParams() : 0;
423 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
425 // Linux ABI treats var-arg calls the same way as regular ones.
541 // Build a sequence of copy-to-reg nodes chained together with token
576 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
579 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
606 // The target-independent code calls getFrameRegister before setting it, and
626 /// form a post-indexed load / store.
633 EVT VT = LSN->getMemoryVT();
644 if (Op->getOpcode() != ISD::ADD)
646 Base = Op->getOperand(0);
647 Offset = Op->getOperand(1);
652 int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
653 return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
675 if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
676 --NumOps; // Ignore the flag operand.
694 for (; NumVals; --NumVals, ++i) {
695 Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
723 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
724 // is marked as having side-effects, while the register read on Hexagon does
735 // Custom-handle ISD::READSTEADYCOUNTER because the target-independent SDNode
736 // is marked as having side-effects, while the register read on Hexagon does
770 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
772 unsigned A = AlignConst->getSExtValue();
780 Size.getNode()->dump(&DAG);
800 // Linux ABI treats var-arg calls the same way as regular ones.
807 MF.getFunction().getFunctionType()->getNumParams());
825 return Reg - Hexagon::R0 + 1;
827 return (Reg - Hexagon::D0 + 1) * 2;
829 return Reg - Hexagon::V0 + 1;
831 return (Reg - Hexagon::W0 + 1) * 2;
839 HMFI.setFirstNamedArgFrameIndex(-int(MFI.getNumFixedObjects()));
847 // 1. 32- and 64-bit values and HVX vectors are passed directly,
899 // If it's a pass-by-value aggregate, then do not dereference the stack
917 HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1);
918 HMFI.setLastNamedArgFrameIndex(-int(MFI.getNumFixedObjects()));
921 int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg;
931 RegAreaStart = (RegAreaStart + 7) & -8;
968 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
969 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1036 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1037 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1051 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1069 // Comparisons of short integers should use sign-extend, not zero-extend,
1071 // The LLVM default is to use zero-extend arbitrarily in these cases.
1075 // A sign-extend of a truncate of a sign-extend is free.
1079 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
1082 // The type that was sign-extended to get the AssertSext must be
1088 // We have sign-extended loads.
1096 bool IsNegative = C && C->getAPIntValue().isNegative();
1135 if (auto *CV = dyn_cast<ConstantVector>(CPN->getConstVal())) {
1136 if (cast<VectorType>(CV->getType())->getElementType()->isIntegerTy(1)) {
1137 IRBuilder<> IRB(CV->getContext());
1139 unsigned VecLen = CV->getNumOperands();
1143 NewConst.push_back(IRB.getInt8(CV->getOperand(i)->isZeroValue()));
1149 Align Alignment = CPN->getAlign();
1155 if (CPN->isMachineConstantPoolEntry())
1156 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Alignment,
1161 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Alignment, Offset,
1164 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1175 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1206 // Return LR, which contains the return address. Mark it an implicit live-in.
1222 while (Depth--)
1239 auto *GV = GAN->getGlobal();
1240 int64_t Offset = GAN->getOffset();
1247 const GlobalObject *GO = GV->getAliaseeObject();
1270 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1301 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1302 GA->getValueType(0),
1303 GA->getOffset(),
1334 int64_t Offset = GA->getOffset();
1345 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1376 int64_t Offset = GA->getOffset();
1382 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1398 int64_t Offset = GA->getOffset();
1402 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1435 switch (HTM.getTLSModel(GA->getGlobal())) {
1447 //===----------------------------------------------------------------------===//
1449 //===----------------------------------------------------------------------===//
1503 // - indexed loads and stores (pre-/post-incremented),
1504 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1654 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1740 // in case it is a compile-time constant. This is a usability feature to
1748 // Custom-lower load/stores of boolean vectors.
1774 // Custom-lower bitcasts from i8 to v8i1.
1806 // Special handling for half-precision floating point conversions.
1826 // Subtarget-specific operation actions.
1878 // Prefix is: nothing for "slow-math",
1879 // "fast2_" for V5+ fast-math double-precision
1880 // (actually, keep fast-math and fast-math2 separate for now)
1970 unsigned Addr = CA->getZExtValue();
1985 return DI->getKind() == DK_MisalignedTrap;
1999 DAG.getContext()->diagnose(DiagnosticInfoMisalignedTrap(O.str()));
2008 assert(!LS->isIndexed() && "Not expecting indexed ops on constant address");
2010 SDValue Chain = LS->getChain();
2012 if (LS->getOpcode() == ISD::LOAD)
2017 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
2020 unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
2029 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
2035 V = cast<Operator>(V)->getOperand(0);
2037 V = cast<Instruction>(V)->getOperand(0);
2041 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
2045 const BasicBlock *Parent = PN->getParent();
2046 int Idx = -1;
2047 for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
2048 BasicBlock *Blk = PN->getIncomingBlock(i);
2051 Value *BackEdgeVal = PN->getIncomingValue(i);
2068 return PN->getIncomingValue(Idx);
2071 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
2072 // pointer points to, for the bit-reverse load intrinsic. Setting this to
2109 auto &Cont = I.getCalledFunction()->getParent()->getContext();
2113 Type *ElTy = I.getCalledFunction()->getReturnType()->getStructElementType(0);
2136 const Module &M = *I.getParent()->getParent()->getParent();
2138 Type *VecTy = I.getArgOperand(1)->getType();
2190 // Non-HVX bool vectors are relatively cheap.
2221 // Widen non-power-of-2 vectors. Such types cannot be split right now,
2245 return { Addr.getOperand(0), CN->getSExtValue() };
2256 ArrayRef<int> AM = SVN->getMask();
2275 // Normalize the mask so that the first non-negative index comes from
2278 unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
2292 ByteMask.push_back(-1);
2300 // All non-undef (non-negative) indexes are well within [0..127], so they
2301 // fit in a single byte. Build two 64-bit words:
2302 // - MaskIdx where each byte is the corresponding index (for non-negative
2304 // - MaskUnd that has 0xFF for each negative index.
2381 if (SDValue S = cast<BuildVectorSDNode>(Op)->getSplatValue())
2390 // Create a Hexagon-specific node for shifting a vector by an integer.
2432 // No instructions for shifts by non-scalars.
2506 const ConstantInt *CI = CN->getConstantIntValue();
2507 Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2509 const ConstantFP *CF = CN->getConstantFPValue();
2510 APInt A = CF->getValueAPF().bitcastToAPInt();
2537 llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2545 uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2546 Consts[1]->getZExtValue() << 16;
2564 int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2565 (Consts[1]->getZExtValue() & 0xFF) << 8 |
2566 (Consts[2]->getZExtValue() & 0xFF) << 16 |
2567 Consts[3]->getZExtValue() << 24;
2628 llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2653 uint64_t Mask = (1ull << W) - 1;
2655 Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2660 // Build two 32-bit vectors and concatenate.
2695 unsigned Off = IdxN->getZExtValue() * ElemWidth;
2738 // Extracting the lowest bit is a no-op, but it changes the type,
2804 unsigned W = C->getZExtValue() * ValWidth;
2958 // Check if this is a special case or all-0 or all-1.
2966 uint32_t C = CN->getZExtValue();
2976 // shifted by the index of the element into a general-purpose register,
3019 // 32-bit integer, so keep them as i32 to use 32-bit inserts.
3023 for (SDValue P : Op.getNode()->op_values()) {
3092 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
3095 // FIXME: in principle up to 64-bit could be made safe, but it would be very
3097 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
3098 return Ty1->getPrimitiveSizeInBits() <= 32;
3106 MVT MemTy = LN->getMemoryVT().getSimpleVT();
3107 ISD::LoadExtType ET = LN->getExtensionType();
3112 LN->getAddressingMode(), ISD::ZEXTLOAD, MVT::i32, dl, LN->getChain(),
3113 LN->getBasePtr(), LN->getOffset(), LN->getPointerInfo(),
3114 /*MemoryVT*/ MVT::i8, LN->getAlign(), LN->getMemOperand()->getFlags(),
3115 LN->getAAInfo(), LN->getRanges());
3119 Align ClaimAlign = LN->getAlign();
3120 if (!validateConstPtrAlignment(LN->getBasePtr(), ClaimAlign, dl, DAG))
3133 SDValue Ch = cast<LoadSDNode>(LU.getNode())->getChain();
3143 SDValue Val = SN->getValue();
3149 SDValue NS = DAG.getTruncStore(SN->getChain(), dl, TR, SN->getBasePtr(),
3150 MVT::i8, SN->getMemOperand());
3151 if (SN->isIndexed()) {
3152 NS = DAG.getIndexedStore(NS, dl, SN->getBasePtr(), SN->getOffset(),
3153 SN->getAddressingMode());
3158 Align ClaimAlign = SN->getAlign();
3159 if (!validateConstPtrAlignment(SN->getBasePtr(), ClaimAlign, dl, DAG))
3162 MVT StoreTy = SN->getMemoryVT().getSimpleVT();
3175 unsigned HaveAlign = LN->getAlign().value();
3184 // smaller legal loads, do the default (target-independent) expansion.
3187 if (!LN->isUnindexed())
3191 if (allowsMemoryAccessForAlignment(Ctx, DL, LN->getMemoryVT(),
3192 *LN->getMemOperand()))
3201 allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
3216 SDValue Base = LN->getBasePtr();
3217 SDValue Chain = LN->getChain();
3226 BO.second -= BO.second % LoadLen;
3238 if (MachineMemOperand *MMO = LN->getMemOperand()) {
3241 MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen, Align(LoadLen),
3242 MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
3243 MMO->getSuccessOrdering(), MMO->getFailureOrdering());
3265 SDVTList VTs = Op.getNode()->getVTList();
3271 uint64_t VY = CY->getZExtValue();
3273 // X +/- 1
3286 DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
3301 return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
3305 SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
3323 FuncInfo->setHasEHReturn();
3356 Op.getNode()->dumpr(&DAG);
3358 errs() << "Error: check for a non-legal type in this operation\n";
3419 unsigned Opc = N->getOpcode();
3427 // We are only custom-lowering stores to verify the alignment of the
3428 // address if it is a compile-time constant. Since a store can be
3429 // modified during type-legalization (the value being stored may need
3450 switch (N->getOpcode()) {
3457 if (N->getValueType(0) == MVT::i8) {
3458 if (N->getOperand(0).getValueType() == MVT::v8i1) {
3460 N->getOperand(0), DAG);
3484 // fold (truncate (build pair x, y)) -> (truncate x) or x
3504 return DCI.DAG.getConstant(-1, dl, ty(Op));
3513 // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3515 if (Cond->getOpcode() == ISD::XOR) {
3517 if (C1->getOpcode() == HexagonISD::PTRUE) {
3525 // fold (truncate (build pair x, y)) -> (truncate x) or x
3537 // fold (or (shl xx, s), (zext y)) -> (COMBINE (shl xx, s-32), y)
3552 if (Amt && Amt->getZExtValue() >= 32 && ty(Z).getSizeInBits() <= 32) {
3553 unsigned A = Amt->getZExtValue();
3556 DCI.DAG.getConstant(A - 32, dl, MVT::i32));
3575 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3581 //===----------------------------------------------------------------------===//
3583 //===----------------------------------------------------------------------===//
3609 case 'r': // R0-R31
3624 case 'a': // M0-M1
3628 case 'q': // q0-q3
3637 case 'v': // V0-V31
3659 /// isFPImmLegal - Returns true if the target can instruction select the
3667 /// isLegalAddressingMode - Return true if the addressing mode represented by
3672 if (Ty->isSized()) {
3695 Scale = -Scale;
3712 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3717 return Imm >= -512 && Imm <= 511;
3720 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3784 /// determined using generic target-independent logic.
3846 std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3847 // Small-data object, do not shrink.
3852 const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3853 return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3867 Module *M = BB->getParent()->getParent();
3868 unsigned SZ = ValueTy->getPrimitiveSizeInBits();
3869 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3879 /// Perform a store-conditional operation to Addr. Return the status of the
3880 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3885 Module *M = BB->getParent()->getParent();
3886 Type *Ty = Val->getType();
3887 unsigned SZ = Ty->getPrimitiveSizeInBits();
3890 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3899 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3906 return LI->getType()->getPrimitiveSizeInBits() > 64
3914 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64