Lines Matching +full:fsin +full:- +full:enable
1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
52 #define DEBUG_TYPE "mips-isel"
55 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
58 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
122 // f16 is a storage-only type, always promote it to f32. in MipsSETargetLowering()
145 setOperationAction(ISD::FSIN, MVT::f16, Promote); in MipsSETargetLowering()
225 // MIPS32r6 replaces the accumulator-based multiplies with a three register in MipsSETargetLowering()
233 // MIPS32r6 replaces the accumulator-based division/remainder with separate in MipsSETargetLowering()
272 // MIPS64r6 replaces the accumulator-based multiplies with a three register in MipsSETargetLowering()
280 // MIPS32r6 replaces the accumulator-based division/remainder with separate in MipsSETargetLowering()
313 // Enable MSA support for the given integer type and Register class.
367 // Enable MSA support for the given floating-point type and Register class.
410 EVT ResTy = Op->getValueType(0); in lowerSELECT()
416 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
417 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
418 Op->getOperand(2)); in lowerSELECT()
477 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
478 // sign/zero-extension is completely overwritten by the new one performed by
480 // - Removes redundant zero extensions performed by an ISD::AND.
487 SDValue Op0 = N->getOperand(0); in performANDCombine()
488 SDValue Op1 = N->getOperand(1); in performANDCombine()
489 unsigned Op0Opcode = Op0->getOpcode(); in performANDCombine()
494 // -> (MipsVExtractZExt $a, $b, $c) in performANDCombine()
502 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); in performANDCombine()
507 SDValue Op0Op2 = Op0->getOperand(2); in performANDCombine()
508 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); in performANDCombine()
514 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; in performANDCombine()
516 Op0->getVTList(), in performANDCombine()
517 ArrayRef(Ops, Op0->getNumOperands())); in performANDCombine()
531 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
543 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, in isVSplat()
552 // Test whether the given node is an all-ones build_vector.
555 // for an all-ones value. in isVectorAllOnes()
556 if (N->getOpcode() == ISD::BITCAST) in isVectorAllOnes()
557 N = N->getOperand(0); in isVectorAllOnes()
569 // an all-ones value. in isVectorAllOnes()
570 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs)) in isVectorAllOnes()
578 if (N->getOpcode() != ISD::XOR) in isBitwiseInverse()
581 if (isVectorAllOnes(N->getOperand(0))) in isBitwiseInverse()
582 return N->getOperand(1) == OfNode; in isBitwiseInverse()
584 if (isVectorAllOnes(N->getOperand(1))) in isBitwiseInverse()
585 return N->getOperand(0) == OfNode; in isBitwiseInverse()
593 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
594 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
602 EVT Ty = N->getValueType(0); in performORCombine()
607 SDValue Op0 = N->getOperand(0); in performORCombine()
608 SDValue Op1 = N->getOperand(1); in performORCombine()
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) { in performORCombine()
611 SDValue Op0Op0 = Op0->getOperand(0); in performORCombine()
612 SDValue Op0Op1 = Op0->getOperand(1); in performORCombine()
613 SDValue Op1Op0 = Op1->getOperand(0); in performORCombine()
614 SDValue Op1Op1 = Op1->getOperand(1); in performORCombine()
656 // If IfClr is not yet set, try looking for a non-constant match. in performORCombine()
738 // - MaxSteps needs to consider the `VT` of the constant for the current in shouldTransformMulToShiftsAddsSubs()
740 // - Consider to perform this optimization after type legalization. in shouldTransformMulToShiftsAddsSubs()
742 // - Take in account `-Os, -Oz` flags because this optimization in shouldTransformMulToShiftsAddsSubs()
767 if ((Val - Floor).ule(Ceil - Val)) { in shouldTransformMulToShiftsAddsSubs()
769 WorkStack.push_back(Val - Floor); in shouldTransformMulToShiftsAddsSubs()
772 WorkStack.push_back(Ceil - Val); in shouldTransformMulToShiftsAddsSubs()
812 // If |c - floor_c| <= |c - ceil_c|, in genConstMult()
814 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). in genConstMult()
815 if ((C - Floor).ule(Ceil - C)) { in genConstMult()
817 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
821 // If |c - floor_c| > |c - ceil_c|, in genConstMult()
822 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). in genConstMult()
824 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
832 EVT VT = N->getValueType(0); in performMULCombine()
834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) in performMULCombine()
836 C->getAPIntValue(), VT, DAG, Subtarget)) in performMULCombine()
837 return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT, in performMULCombine()
838 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT), in performMULCombine()
852 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); in performDSPShiftCombine()
858 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, in performDSPShiftCombine()
865 return DAG.getNode(Opc, DL, Ty, N->getOperand(0), in performDSPShiftCombine()
872 EVT Ty = N->getValueType(0); in performSHLCombine()
880 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
884 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
885 // sign/zero-extension is completely overwritten by the new one performed by
887 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
895 EVT Ty = N->getValueType(0); in performSRACombine()
898 SDValue Op0 = N->getOperand(0); in performSRACombine()
899 SDValue Op1 = N->getOperand(1); in performSRACombine()
904 // -> (MipsVExtractSExt $a, $b, $c) in performSRACombine()
905 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { in performSRACombine()
906 SDValue Op0Op0 = Op0->getOperand(0); in performSRACombine()
912 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && in performSRACombine()
913 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) in performSRACombine()
916 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); in performSRACombine()
917 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); in performSRACombine()
920 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && in performSRACombine()
922 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), in performSRACombine()
923 Op0Op0->getOperand(2) }; in performSRACombine()
925 Op0Op0->getVTList(), in performSRACombine()
926 ArrayRef(Ops, Op0Op0->getNumOperands())); in performSRACombine()
941 EVT Ty = N->getValueType(0); in performSRLCombine()
968 EVT Ty = N->getValueType(0); in performSETCCCombine()
973 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) in performSETCCCombine()
976 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), in performSETCCCombine()
977 N->getOperand(1), N->getOperand(2)); in performSETCCCombine()
981 EVT Ty = N->getValueType(0); in performVSELECTCombine()
984 SDValue SetCC = N->getOperand(0); in performVSELECTCombine()
991 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
999 EVT Ty = N->getValueType(0); in performXORCombine()
1005 SDValue Op0 = N->getOperand(0); in performXORCombine()
1006 SDValue Op1 = N->getOperand(1); in performXORCombine()
1016 if (NotOp->getOpcode() == ISD::OR) in performXORCombine()
1017 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), in performXORCombine()
1018 NotOp->getOperand(1)); in performXORCombine()
1029 switch (N->getOpcode()) { in PerformDAGCombine()
1057 N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n"; in PerformDAGCombine()
1058 Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n"); in PerformDAGCombine()
1186 Nd.getAlign(), Nd.getMemOperand()->getFlags()); in lowerLOAD()
1192 commonAlignment(Nd.getAlign(), 4), Nd.getMemOperand()->getFlags()); in lowerLOAD()
1222 Nd.getMemOperand()->getFlags(), Nd.getAAInfo()); in lowerSTORE()
1228 Nd.getMemOperand()->getFlags(), Nd.getAAInfo()); in lowerSTORE()
1296 // This function expands mips intrinsic nodes which have 64-bit input operands
1299 // out64 = intrinsic-node in64
1301 // lo = copy (extract-element (in64, 0))
1302 // hi = copy (extract-element (in64, 1))
1303 // mips-specific-node
1306 // out64 = merge-values (v0, v1)
1310 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; in lowerDSPIntr()
1316 Ops.push_back(Op->getOperand(OpNo++)); in lowerDSPIntr()
1319 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); in lowerDSPIntr()
1322 SDValue Opnd = Op->getOperand(++OpNo), In64; in lowerDSPIntr()
1330 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) in lowerDSPIntr()
1331 Ops.push_back(Op->getOperand(OpNo)); in lowerDSPIntr()
1340 for (EVT Ty : Op->values()) in lowerDSPIntr()
1350 assert(Val->getValueType(1) == MVT::Other); in lowerDSPIntr()
1358 SDValue Vec = Op->getOperand(1); in lowerMSACopyIntr()
1359 SDValue Idx = Op->getOperand(2); in lowerMSACopyIntr()
1360 EVT ResTy = Op->getValueType(0); in lowerMSACopyIntr()
1361 EVT EltTy = Vec->getValueType(0).getVectorElementType(); in lowerMSACopyIntr()
1370 EVT ResVecTy = Op->getValueType(0); in lowerMSASplatZExt()
1376 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating in lowerMSASplatZExt()
1378 SDValue LaneA = Op->getOperand(OpNr); in lowerMSASplatZExt()
1387 // value as the lower - this results in the BUILD_VECTOR node not being in lowerMSASplatZExt()
1415 auto *CImm = cast<ConstantSDNode>(Op->getOperand(ImmOp)); in lowerMSASplatImm()
1417 APInt(Op->getValueType(0).getScalarType().getSizeInBits(), in lowerMSASplatImm()
1418 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned), in lowerMSASplatImm()
1419 SDLoc(Op), Op->getValueType(0)); in lowerMSASplatImm()
1461 EVT VecTy = Op->getValueType(0); in lowerMSABinaryBitImmIntr()
1469 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue(); in lowerMSABinaryBitImmIntr()
1489 // only values 0-63 are valid. in lowerMSABinaryBitImmIntr()
1499 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm); in lowerMSABinaryBitImmIntr()
1504 EVT ResTy = Op->getValueType(0); in truncateVecElts()
1505 SDValue Vec = Op->getOperand(2); in truncateVecElts()
1508 SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1, in truncateVecElts()
1516 EVT ResTy = Op->getValueType(0); in lowerMSABitClear()
1521 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), in lowerMSABitClear()
1527 EVT ResTy = Op->getValueType(0); in lowerMSABitClearImm()
1529 << Op->getConstantOperandAPInt(2); in lowerMSABitClearImm()
1532 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); in lowerMSABitClearImm()
1538 unsigned Intrinsic = Op->getConstantOperandVal(0); in lowerINTRINSIC_WO_CHAIN()
1578 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1579 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1584 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1587 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1588 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1590 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1606 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear) in lowerINTRINSIC_WO_CHAIN()
1607 EVT VecTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1609 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) in lowerINTRINSIC_WO_CHAIN()
1612 Op->getConstantOperandVal(3) + 1); in lowerINTRINSIC_WO_CHAIN()
1615 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1621 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear) in lowerINTRINSIC_WO_CHAIN()
1622 EVT VecTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1624 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) in lowerINTRINSIC_WO_CHAIN()
1627 Op->getConstantOperandVal(3) + 1); in lowerINTRINSIC_WO_CHAIN()
1630 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1633 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1634 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1636 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1637 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), in lowerINTRINSIC_WO_CHAIN()
1638 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1640 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1641 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1643 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1644 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1645 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1650 EVT VecTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1653 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1661 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), in lowerINTRINSIC_WO_CHAIN()
1667 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1668 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1670 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1671 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1673 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear) in lowerINTRINSIC_WO_CHAIN()
1674 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1675 Op->getOperand(1), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1676 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1678 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear) in lowerINTRINSIC_WO_CHAIN()
1679 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1680 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG), in lowerINTRINSIC_WO_CHAIN()
1681 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1686 EVT VecTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1689 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1697 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), in lowerINTRINSIC_WO_CHAIN()
1703 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1704 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1706 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1707 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1712 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1713 Op->getOperand(2), ISD::SETEQ); in lowerINTRINSIC_WO_CHAIN()
1718 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1724 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1725 Op->getOperand(2), ISD::SETLE); in lowerINTRINSIC_WO_CHAIN()
1730 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1736 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1737 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1742 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1748 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1749 Op->getOperand(2), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
1754 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1760 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1761 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1766 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1780 Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1781 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1796 // behaviour since i64 is only illegal when the register file is 32-bit. in lowerINTRINSIC_WO_CHAIN()
1798 Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1799 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1805 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1806 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1811 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1812 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1815 // TODO: If intrinsics have fast-math-flags, propagate them. in lowerINTRINSIC_WO_CHAIN()
1816 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1817 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1821 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1822 Op->getOperand(2), ISD::SETOEQ); in lowerINTRINSIC_WO_CHAIN()
1825 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1826 Op->getOperand(2), ISD::SETOLE); in lowerINTRINSIC_WO_CHAIN()
1829 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1830 Op->getOperand(2), ISD::SETOLT); in lowerINTRINSIC_WO_CHAIN()
1833 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1834 Op->getOperand(2), ISD::SETONE); in lowerINTRINSIC_WO_CHAIN()
1837 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1838 Op->getOperand(2), ISD::SETO); in lowerINTRINSIC_WO_CHAIN()
1841 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1842 Op->getOperand(2), ISD::SETUEQ); in lowerINTRINSIC_WO_CHAIN()
1845 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1846 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1849 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1850 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1853 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1854 Op->getOperand(2), ISD::SETUO); in lowerINTRINSIC_WO_CHAIN()
1857 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1858 Op->getOperand(2), ISD::SETUNE); in lowerINTRINSIC_WO_CHAIN()
1861 // TODO: If intrinsics have fast-math-flags, propagate them. in lowerINTRINSIC_WO_CHAIN()
1862 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1863 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1866 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1867 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1870 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1871 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1876 EVT ResTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1878 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1886 // TODO: If intrinsics have fast-math-flags, propagate them. in lowerINTRINSIC_WO_CHAIN()
1887 EVT ResTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1889 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1890 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
1894 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1897 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1898 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1901 // TODO: If intrinsics have fast-math-flags, propagate them. in lowerINTRINSIC_WO_CHAIN()
1902 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1903 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1906 // TODO: If intrinsics have fast-math-flags, propagate them. in lowerINTRINSIC_WO_CHAIN()
1907 return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1908 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1912 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1915 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1918 // TODO: If intrinsics have fast-math-flags, propagate them. in lowerINTRINSIC_WO_CHAIN()
1919 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1920 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1923 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1924 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1927 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1928 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1933 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1934 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1939 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1940 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1945 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1946 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1951 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1952 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1957 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1958 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1972 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); in lowerINTRINSIC_WO_CHAIN()
1975 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1976 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1986 EVT ResTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1987 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1989 Op->getOperand(2), Op->getOperand(3))); in lowerINTRINSIC_WO_CHAIN()
1995 EVT ResTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
1996 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1998 Op->getOperand(2), Op->getOperand(3))); in lowerINTRINSIC_WO_CHAIN()
2004 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2005 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2010 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2011 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2016 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2017 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); in lowerINTRINSIC_WO_CHAIN()
2022 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2023 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2028 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2029 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2034 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2035 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2040 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2041 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); in lowerINTRINSIC_WO_CHAIN()
2046 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2047 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2052 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2053 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2058 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2059 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2064 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2065 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2070 EVT ResTy = Op->getValueType(0); in lowerINTRINSIC_WO_CHAIN()
2071 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2073 Op->getOperand(2), Op->getOperand(3))); in lowerINTRINSIC_WO_CHAIN()
2079 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2081 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2082 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2083 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
2086 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2087 Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2089 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
2092 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2093 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2095 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2096 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2101 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2102 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2107 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2108 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2113 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2135 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); in lowerINTRINSIC_WO_CHAIN()
2143 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); in lowerINTRINSIC_WO_CHAIN()
2146 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2147 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2162 int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue(); in lowerINTRINSIC_WO_CHAIN()
2171 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2177 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2178 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2187 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2188 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2189 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2194 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2195 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2196 Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2201 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2207 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2208 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2222 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); in lowerINTRINSIC_WO_CHAIN()
2231 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2237 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2238 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2252 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); in lowerINTRINSIC_WO_CHAIN()
2261 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2262 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2267 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2268 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2273 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2274 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
2276 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2277 Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
2279 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2280 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); in lowerINTRINSIC_WO_CHAIN()
2291 SDValue ChainIn = Op->getOperand(0); in lowerMSALoadIntr()
2292 SDValue Address = Op->getOperand(2); in lowerMSALoadIntr()
2293 SDValue Offset = Op->getOperand(3); in lowerMSALoadIntr()
2294 EVT ResTy = Op->getValueType(0); in lowerMSALoadIntr()
2295 EVT PtrTy = Address->getValueType(0); in lowerMSALoadIntr()
2310 unsigned Intr = Op->getConstantOperandVal(1); in lowerINTRINSIC_W_CHAIN()
2365 SDValue ChainIn = Op->getOperand(0); in lowerMSAStoreIntr()
2366 SDValue Value = Op->getOperand(2); in lowerMSAStoreIntr()
2367 SDValue Address = Op->getOperand(3); in lowerMSAStoreIntr()
2368 SDValue Offset = Op->getOperand(4); in lowerMSAStoreIntr()
2369 EVT PtrTy = Address->getValueType(0); in lowerMSAStoreIntr()
2385 unsigned Intr = Op->getConstantOperandVal(1); in lowerINTRINSIC_VOID()
2399 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2400 // choose to sign-extend but we could have equally chosen zero-extend. The
2402 // result into this node later (possibly changing it to a zero-extend in the
2407 EVT ResTy = Op->getValueType(0); in lowerEXTRACT_VECTOR_ELT()
2408 SDValue Op0 = Op->getOperand(0); in lowerEXTRACT_VECTOR_ELT()
2409 EVT VecTy = Op0->getValueType(0); in lowerEXTRACT_VECTOR_ELT()
2415 SDValue Op1 = Op->getOperand(1); in lowerEXTRACT_VECTOR_ELT()
2425 if (Op->isUndef()) in isConstantOrUndef()
2435 for (unsigned i = 0; i < Op->getNumOperands(); ++i) in isConstantOrUndefBUILD_VECTOR()
2436 if (isConstantOrUndef(Op->getOperand(i))) in isConstantOrUndefBUILD_VECTOR()
2445 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2446 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2448 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2450 // signed 10-bit immediate
2451 // - Non-constant splats are legal as-is.
2452 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2453 // - All others are illegal and must be expanded.
2457 EVT ResTy = Op->getValueType(0); in lowerBUILD_VECTOR()
2466 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, in lowerBUILD_VECTOR()
2469 // We can only cope with 8, 16, 32, or 64-bit elements in lowerBUILD_VECTOR()
2495 // There's no fill.d to fall back on for 64-bit values in lowerBUILD_VECTOR()
2513 EVT ResTy = Node->getValueType(0); in lowerBUILD_VECTOR()
2521 Node->getOperand(i), in lowerBUILD_VECTOR()
2551 int SHFIndices[4] = { -1, -1, -1, -1 }; in lowerVECTOR_SHUFFLE_SHF()
2560 // Convert from vector index to 4-element subvector index in lowerVECTOR_SHUFFLE_SHF()
2562 if (Idx != -1) { in lowerVECTOR_SHUFFLE_SHF()
2563 Idx -= 4 * (j / 4); in lowerVECTOR_SHUFFLE_SHF()
2570 if (SHFIndices[i] == -1) in lowerVECTOR_SHUFFLE_SHF()
2573 // Check that non-undef values are the same as in the mask. If they in lowerVECTOR_SHUFFLE_SHF()
2575 if (!(Idx == -1 || Idx == SHFIndices[i])) in lowerVECTOR_SHUFFLE_SHF()
2582 for (int i = 3; i >= 0; --i) { in lowerVECTOR_SHUFFLE_SHF()
2585 if (Idx == -1) in lowerVECTOR_SHUFFLE_SHF()
2595 Op->getOperand(0)); in lowerVECTOR_SHUFFLE_SHF()
2609 if (*I != -1 && *I != ExpectedIndex) in fitsRegularPattern()
2634 int SplatIndex = -1; in isVECTOR_SHUFFLE_SPLATI()
2636 if (V != -1) { in isVECTOR_SHUFFLE_SPLATI()
2674 Wt = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVEV()
2676 Wt = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVEV()
2683 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVEV()
2685 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVEV()
2720 Wt = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVOD()
2722 Wt = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVOD()
2729 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVOD()
2731 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVOD()
2740 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2764 // Check even elements are taken from the right (lowest-indexed) elements of in lowerVECTOR_SHUFFLE_ILVR()
2767 Wt = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVR()
2769 Wt = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVR()
2773 // Check odd elements are taken from the right (lowest-indexed) elements of in lowerVECTOR_SHUFFLE_ILVR()
2776 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVR()
2778 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVR()
2787 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2812 // Check even elements are taken from the left (highest-indexed) elements of in lowerVECTOR_SHUFFLE_ILVL()
2815 Wt = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVL()
2817 Wt = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVL()
2821 // Check odd elements are taken from the left (highest-indexed) elements of in lowerVECTOR_SHUFFLE_ILVL()
2824 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVL()
2827 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVL()
2861 Wt = Op->getOperand(0); in lowerVECTOR_SHUFFLE_PCKEV()
2863 Wt = Op->getOperand(1); in lowerVECTOR_SHUFFLE_PCKEV()
2868 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_PCKEV()
2870 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_PCKEV()
2904 Wt = Op->getOperand(0); in lowerVECTOR_SHUFFLE_PCKOD()
2906 Wt = Op->getOperand(1); in lowerVECTOR_SHUFFLE_PCKOD()
2911 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_PCKOD()
2913 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_PCKOD()
2942 // Idx == -1 means UNDEF in lowerVECTOR_SHUFFLE_VSHF()
2957 Op0 = Op->getOperand(0); in lowerVECTOR_SHUFFLE_VSHF()
2958 Op1 = Op->getOperand(1); in lowerVECTOR_SHUFFLE_VSHF()
2960 Op0 = Op1 = Op->getOperand(0); in lowerVECTOR_SHUFFLE_VSHF()
2962 Op0 = Op1 = Op->getOperand(1); in lowerVECTOR_SHUFFLE_VSHF()
2967 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11> in lowerVECTOR_SHUFFLE_VSHF()
2969 // <0b00, 0b01> + <0b10, 0b11> -> in lowerVECTOR_SHUFFLE_VSHF()
2970 // 0b0100 + 0b1110 -> 0b01001110 in lowerVECTOR_SHUFFLE_VSHF()
2981 EVT ResTy = Op->getValueType(0); in lowerVECTOR_SHUFFLE()
2990 Indices.push_back(Node->getMaskElt(i)); in lowerVECTOR_SHUFFLE()
3030 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32()
3034 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in emitBPOSGE32()
3036 MachineFunction *F = BB->getParent(); in emitBPOSGE32()
3037 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); in emitBPOSGE32()
3038 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); in emitBPOSGE32()
3039 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); in emitBPOSGE32()
3040 F->insert(It, FBB); in emitBPOSGE32()
3041 F->insert(It, TBB); in emitBPOSGE32()
3042 F->insert(It, Sink); in emitBPOSGE32()
3045 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), in emitBPOSGE32()
3046 BB->end()); in emitBPOSGE32()
3047 Sink->transferSuccessorsAndUpdatePHIs(BB); in emitBPOSGE32()
3050 BB->addSuccessor(FBB); in emitBPOSGE32()
3051 BB->addSuccessor(TBB); in emitBPOSGE32()
3052 FBB->addSuccessor(Sink); in emitBPOSGE32()
3053 TBB->addSuccessor(Sink); in emitBPOSGE32()
3056 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); in emitBPOSGE32()
3058 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB); in emitBPOSGE32()
3062 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
3064 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); in emitBPOSGE32()
3068 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3072 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), in emitBPOSGE32()
3099 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo()
3103 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in emitMSACBranchPseudo()
3105 MachineFunction *F = BB->getParent(); in emitMSACBranchPseudo()
3106 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); in emitMSACBranchPseudo()
3107 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); in emitMSACBranchPseudo()
3108 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); in emitMSACBranchPseudo()
3109 F->insert(It, FBB); in emitMSACBranchPseudo()
3110 F->insert(It, TBB); in emitMSACBranchPseudo()
3111 F->insert(It, Sink); in emitMSACBranchPseudo()
3114 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), in emitMSACBranchPseudo()
3115 BB->end()); in emitMSACBranchPseudo()
3116 Sink->transferSuccessorsAndUpdatePHIs(BB); in emitMSACBranchPseudo()
3119 BB->addSuccessor(FBB); in emitMSACBranchPseudo()
3120 BB->addSuccessor(TBB); in emitMSACBranchPseudo()
3121 FBB->addSuccessor(Sink); in emitMSACBranchPseudo()
3122 TBB->addSuccessor(Sink); in emitMSACBranchPseudo()
3125 BuildMI(BB, DL, TII->get(BranchOp)) in emitMSACBranchPseudo()
3131 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
3133 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); in emitMSACBranchPseudo()
3137 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
3141 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), in emitMSACBranchPseudo()
3166 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW()
3175 // We must copy to an even-numbered MSA register so that the in emitCOPY_FW()
3176 // single-precision sub-register is also guaranteed to be even-numbered. in emitCOPY_FW()
3179 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws); in emitCOPY_FW()
3182 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); in emitCOPY_FW()
3188 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); in emitCOPY_FW()
3189 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); in emitCOPY_FW()
3212 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD()
3219 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); in emitCOPY_FD()
3223 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); in emitCOPY_FD()
3224 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); in emitCOPY_FD()
3241 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitINSERT_FW()
3251 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FW()
3255 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) in emitINSERT_FW()
3277 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitINSERT_FD()
3285 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FD()
3289 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) in emitINSERT_FD()
3323 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitINSERT_DF_VIDX()
3370 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_DF_VIDX()
3380 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
3388 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1) in emitINSERT_DF_VIDX()
3396 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2) in emitINSERT_DF_VIDX()
3403 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2) in emitINSERT_DF_VIDX()
3413 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB), in emitINSERT_DF_VIDX()
3417 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd) in emitINSERT_DF_VIDX()
3437 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitFILL_FW()
3448 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); in emitFILL_FW()
3449 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) in emitFILL_FW()
3453 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); in emitFILL_FW()
3472 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitFILL_FD()
3479 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); in emitFILL_FD()
3480 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) in emitFILL_FD()
3484 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); in emitFILL_FD()
3506 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitST_F16_PSEUDO()
3523 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0); in emitST_F16_PSEUDO()
3526 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp) in emitST_F16_PSEUDO()
3532 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64)) in emitST_F16_PSEUDO()
3536 .addMemOperand(BB->getParent()->getMachineMemOperand( in emitST_F16_PSEUDO()
3550 // Safety: We can't use ld.h & co as they over-read from the source.
3561 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitLD_F16_PSEUDO()
3577 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt); in emitLD_F16_PSEUDO()
3583 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32); in emitLD_F16_PSEUDO()
3587 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt); in emitLD_F16_PSEUDO()
3604 // the correct register class. That requires operands be tie-able across
3637 // undef bits are "just right" and the exception enable bits are
3660 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitFPROUND_PSEUDO()
3671 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs); in emitFPROUND_PSEUDO()
3672 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp); in emitFPROUND_PSEUDO()
3677 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs); in emitFPROUND_PSEUDO()
3680 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2) in emitFPROUND_PSEUDO()
3684 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3) in emitFPROUND_PSEUDO()
3693 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2) in emitFPROUND_PSEUDO()
3699 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI); in emitFPROUND_PSEUDO()
3716 // the correct register class. That requires operands be tie-able across
3765 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitFPEXTEND_PSEUDO()
3776 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws); in emitFPEXTEND_PSEUDO()
3779 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp); in emitFPEXTEND_PSEUDO()
3787 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0); in emitFPEXTEND_PSEUDO()
3788 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp); in emitFPEXTEND_PSEUDO()
3792 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2) in emitFPEXTEND_PSEUDO()
3795 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd) in emitFPEXTEND_PSEUDO()
3814 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitFEXP2_W_1()
3821 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); in emitFEXP2_W_1()
3822 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); in emitFEXP2_W_1()
3825 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg()) in emitFEXP2_W_1()
3843 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitFEXP2_D_1()
3850 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); in emitFEXP2_D_1()
3851 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); in emitFEXP2_D_1()
3854 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg()) in emitFEXP2_D_1()