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/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dufs-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-commo
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H A Dcdns,ufshc.txt3 UFS nodes are defined to describe on-chip UFS host controllers.
5 Please see the ufshcd-pltfrm.txt for a list of all available properties.
8 - compatible : Compatible list, contains one of the following controllers:
9 "cdns,ufshc" - Generic CDNS HCI,
10 "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY
12 "jedec,ufs-2.0"
14 - reg : Address and length of the UFS register set.
15 - interrupts : One interrupt mapping.
16 - freq-table-hz : Clock frequency table.
17 See the ufshcd-pltfrm.txt for details.
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H A Dufs-mediatek.txt3 UFS nodes are defined to describe on-chip UFS hardware macro.
7 contain a phandle reference to UFS M-PHY node.
10 - compatible : Compatible list, contains the following controller:
11 "mediatek,mt8183-ufshci" for MediaTek UFS host controller
13 "mediatek,mt8192-ufshci" for MediaTek UFS host controller
15 - reg : Address and length of the UFS register set.
16 - phys : phandle to m-phy.
17 - clocks : List of phandle and clock specifier pairs.
18 - clock-names : List of clock input name strings sorted in the same
21 - freq-table-hz : Array of <min max> operating frequencies stored in the same
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H A Dufs-hisi.txt3 UFS nodes are defined to describe on-chip UFS hardware macro.
7 - compatible : compatible list, contains one of the following -
8 "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
10 "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
12 - reg : should contain UFS register address space & UFS SYS CTRL register address,
13 - interrupts : interrupt number
14 - clocks : List of phandle and clock specifier pairs
15 - clock-names : List of clock input name strings sorted in the same
17 - freq-table-hz : Array of <min max> operating frequencies stored in the same
22 - resets : describe reset node register
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H A Dufshcd-pltfrm.txt3 UFSHC nodes are defined to describe on-chip UFS host controllers.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
10 SoC-specific compatible along with "qcom,ufshc" and
12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16 "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
17 "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
18 "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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H A Dmediatek,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stanley Chu <stanley.chu@mediatek.com>
13 - $ref: ufs-common.yaml
18 - mediatek,mt8183-ufshci
19 - mediatek,mt8192-ufshci
24 clock-names:
26 - const: ufs
34 vcc-supply: true
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H A Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
24 - $ref: ufs-common.yaml
29 - enum:
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H A Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
25 clock-names:
27 - const: fck
28 - const: ref_clk
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H A Dhisilicon,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
21 - compatible
24 - $ref: ufs-common.yaml
29 - items:
30 - const: hisilicon,hi3660-ufs
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/freebsd/sys/dev/cpufreq/
H A Dcpufreq_dt.c1 /*-
61 uint64_t freq; member
71 #define CPUFREQ_DT_HAVE_REGULATOR(sc) ((sc)->reg != NULL)
86 cpufreq_dt_notify(device_t dev, uint64_t freq) in cpufreq_dt_notify() argument
95 if (CPU_ISSET(cpu, &sc->cpus)) { in cpufreq_dt_notify()
97 pc->pc_clock = freq; in cpufreq_dt_notify()
103 cpufreq_dt_find_opp(device_t dev, uint64_t freq) in cpufreq_dt_find_opp() argument
113 DPRINTF(dev, "Looking for freq %ju\n", freq); in cpufreq_dt_find_opp()
114 for (n = 0; n < sc->nopp; n++) { in cpufreq_dt_find_opp()
115 diff = abs64((int64_t)sc->opp[n].freq - (int64_t)freq); in cpufreq_dt_find_opp()
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
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H A Dsm6350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
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H A Dsm6375.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
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H A Dsc8180x.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8180x.h>
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H A Dsm8150.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
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H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp.txt2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
21 freq: clock frequency in kHz
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 operating-points = <
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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/freebsd/contrib/ntp/util/
H A Dtg.c6 * broadcast timecode. Alternatively, it can generate the IRIG-B
24 * over the range 0-255. The signal generator by default uses WWV
26 * switches to IRIG-B format.
42 * the transmissionorder is low-order first as the frame is processed
44 * For IRIG the on-time marker M preceeds the first (units) bit, so its
64 #define SECOND 8000 /* one second of 125-us samples */
68 #define IRIG 1 /* IRIG-B encoder */
80 * Companded sine table amplitude 3000 units
82 int c3000[] = {1, 48, 63, 70, 78, 82, 85, 89, 92, 94, /* 0-9 */
83 96, 98, 99, 100, 101, 101, 102, 103, 103, 103, /* 10-19 */
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/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_subr.c1 /*-
2 * SPDX-License-Identifier: ISC
10 * distributed with the Asus RT-N16 firmware source code release.
41 if (_sc->dev != NULL) \
42 device_printf(_sc->dev, _fmt, ##__VA_ARGS__); \
91 ((uint8_t)BHND_PMU_GET_BITS((_sc)->caps, BHND_PMU_CAP_REV))
94 bhnd_core_clkctl_wait((_sc)->clkctl, (_val), (_mask))
100 CHIPC_CST4330_CHIPMODE_SDIOD((_sc)->io->rd_chipst((_sc)->io_ctx))
113 * @retval non-zero if the query state could not be initialized.
119 query->dev = dev; in bhnd_pmu_query_init()
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/freebsd/contrib/ntp/ntpd/
H A Drefclock_wwv.c2 * refclock_wwv - clock driver for NIST WWV/H time/frequency station
43 * kHz and mu-law companding. This is the same standard as used by the
53 * Report 97-8-1, University of Delaware, August 1997, 25 pp., available
61 * a nonzero ICOM ID select code. The C-IV trace is turned on if the
68 * port, where 0 is the mike port (default) and 1 is the line-in port.
74 * CEVNT_PROP propagation failure - no stations heard
82 #define PRECISION (-10) /* precision assumed (about 1 ms) */
84 #define WWV_SEC 8000 /* second epoch (sample rate) (Hz) */
87 #define SIZE 256 /* decompanding table siz
514 double phase, freq; /* logical clock phase and frequency */ global() member
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H A Drefclock_irig.c2 * refclock_irig - audio IRIG-B/E demodulator/decoder
26 * Audio IRIG-B/E demodulator/decoder
29 * IRIG-B/E signals commonly produced by GPS receivers and other timing
30 * devices. The IRIG signal is an amplitude-modulated carrier with
31 * pulse-width modulated data bits. For IRIG-B, the carrier frequency is
32 * 1000 Hz and bit rate 100 b/s; for IRIG-E, the carrier frequenchy is
33 * 100 Hz an
216 double phase, freq; /* logical clock phase and frequency */ global() member
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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