/linux/drivers/firmware/arm_scmi/ |
H A D | perf.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2018-2023 ARM Ltd. 8 #define pr_fmt(fmt) "SCMI Notifications PERF - " fmt 86 __le32 domain; member 91 __le32 domain; member 102 __le32 domain; member 107 __le32 domain; member 175 if (_opp->indicative_freq == f_) \ 203 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, in scmi_perf_attributes_get() 208 attr = t->rx.buf; in scmi_perf_attributes_get() [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sm4450.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,sm4450-camcc.h> 8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h> 9 #include <dt-bindings/clock/qcom,sm4450-gcc.h> 10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/power/qcom,rpmhpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h> [all …]
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H A D | sdm670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 12 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 14 #include <dt-bindings/clock/qcom,rpmh.h> 15 #include <dt-bindings/dma/qcom-gpi.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/interconnect/qcom,osm-l3.h> [all …]
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H A D | qdu1000.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 7 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/dma/qcom-gpi.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interconnect/qcom,icc.h> 11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> [all …]
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H A D | sm6115.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7 #include <dt-bindings/clock/qcom,gcc-sm6115.h> 8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h> 9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h> 11 #include <dt-bindings/dma/qcom-gpi.h> 12 #include <dt-bindings/firmware/qcom,scm.h> 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/interconnect/qcom,rpm-icc.h> [all …]
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/linux/include/linux/ |
H A D | energy_model.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 15 * struct em_perf_state - Performance state of a performance domain 43 * struct em_perf_table - Performance states table 55 * struct em_perf_domain - Performance domain 61 * @cpus: Cpumask covering the CPUs of the domain. It's here 66 * In case of CPU device, a "performance domain" represents a group of CPUs 67 * whose performance is scaled together. All CPUs of a performance domain 68 * must have the same micro-architecture. Performance domains often have 69 * a 1-to-1 mapping with CPUFreq policies. In case of other devices the @cpus 84 * EM_PERF_DOMAIN_MICROWATTS: The power values are in micro-Watts or some [all …]
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H A D | scpi_protocol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 14 u32 freq; member 40 * struct scpi_ops - represents the various operations provided 44 * @clk_get_range: gets clock range limit(min - max in Hz) 48 * @dvfs_get_idx: gets the Operating Point of the given power domain. 50 * @dvfs_set_idx: sets the Operating Point of the given power domain. 53 * domain. It includes the OPP list and the latency information 54 * @device_domain_id: gets the scpi domain id for a given device 60 * @device_get_power_state: gets the power state of a power domain 61 * @device_set_power_state: sets the power state of a power domain
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | base.c | 42 u8 pstate, u8 domain, u32 input) in nvkm_clk_adjust() argument 44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust() 62 if (subd && boostS.domain == domain) { in nvkm_clk_adjust() 76 * C-States 82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid() local 83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid() 86 while (domain && domain->name != nv_clk_src_max) { in nvkm_cstate_valid() 87 if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) { in nvkm_cstate_valid() 88 u32 freq = cstate->domain[domain->name]; in nvkm_cstate_valid() local 89 switch (clk->boost_mode) { in nvkm_cstate_valid() [all …]
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H A D | gf100.c | 33 u32 freq; member 51 struct nvkm_device *device = clk->base.subdev.device; in read_vco() 54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco() 55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco() 61 struct nvkm_device *device = clk->base.subdev.device; in read_pll() 75 sclk = device->crystal; in read_pll() 79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll() 82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll() 100 struct nvkm_device *device = clk->base.subdev.device; in read_div() 107 return device->crystal; in read_div() [all …]
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H A D | gk104.c | 33 u32 freq; member 52 struct nvkm_device *device = clk->base.subdev.device; in read_vco() 62 struct nvkm_device *device = clk->base.subdev.device; in read_pll() 77 sclk = device->crystal; in read_pll() 108 struct nvkm_device *device = clk->base.subdev.device; in read_div() 115 return device->crystal; in read_div() 135 struct nvkm_device *device = clk->base.subdev.device; in read_mem() 147 struct nvkm_device *device = clk->base.subdev.device; in read_clk() 192 struct nvkm_subdev *subdev = &clk->base.subdev; in gk104_clk_read() 193 struct nvkm_device *device = subdev->device; in gk104_clk_read() [all …]
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H A D | nv50.c | 34 struct nvkm_device *device = clk->base.subdev.device; in read_div() 35 switch (device->chipset) { in read_div() 54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src() 55 struct nvkm_device *device = subdev->device; in read_pll_src() 56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src() 60 switch (device->chipset) { in read_pll_src() 103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src() 104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src() 127 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_ref() 128 struct nvkm_device *device = subdev->device; in read_pll_ref() [all …]
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/linux/drivers/net/wireless/ath/ |
H A D | dfs_pattern_detector.c | 25 * struct radar_types - contains array of patterns defined for one DFS domain 38 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100) 43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100) 49 (PRF2PRI(PMAX) - PRI_TOLERANCE), \ 54 /* radar types as defined by ETSI EN-301-893 v1.5.1 */ 74 PMIN - PRI_TOLERANCE, \ 106 PMIN - PRI_TOLERANCE, \ 135 * get_dfs_domain_radar_types() - get radar types for a given DFS domain 138 * Return value: radar_types ptr on success, NULL if DFS domain is not supported 145 if (dfs_domains[i]->region == region) in get_dfs_domain_radar_types() [all …]
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H A D | dfs_pattern_detector.h | 25 * TODO: this might need to be HW-dependent 30 * struct ath_dfs_pool_stats - DFS Statistics for global pools 43 * struct pulse_event - describing pulses reported by PHY 45 * @freq: channel frequency in MHz 52 u16 freq; member 59 * struct radar_detector_specs - detector specs for a radar pattern type 85 * struct dfs_pattern_detector - DFS pattern detector 87 * @set_dfs_domain(): set DFS domain, resets detector lines upon domain changes 115 * dfs_pattern_detector_init() - constructor for pattern detector class 116 * @param region: DFS domain to be used, can be NL80211_DFS_UNSET at creation
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/linux/kernel/power/ |
H A D | energy_model.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2018-2021, Arm ltd. 34 return (dev->bus == &cpu_subsys); in _is_cpu_device() 48 struct em_dbg_info *em_dbg = s->private; \ 53 table = em_perf_state_from_pd(em_dbg->pd); \ 54 val = table[em_dbg->ps_id].name; \ 73 unsigned long freq; in em_debug_create_ps() local 82 freq = table[i].frequency; in em_debug_create_ps() 85 snprintf(name, sizeof(name), "ps:%lu", freq); in em_debug_create_ps() 87 /* Create per-ps directory */ in em_debug_create_ps() [all …]
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/linux/drivers/cpufreq/ |
H A D | scmi-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2018-2021 ARM Ltd. 11 #include <linux/clk-provider.h> 50 priv = policy->driver_data; in scmi_cpufreq_get_rate() 52 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate() 59 * perf_ops->freq_set is not a synchronous, the actual OPP change will 66 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target() 67 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target() local 69 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target() 75 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch() [all …]
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H A D | mediatek-cpufreq-hw.c | 1 // SPDX-License-Identifier: GPL-2.0 74 priv->fdvfs = devm_of_iomap(priv->dev, priv->dev->of_node, 0, NULL); in mtk_cpufreq_hw_mt8196_init() 75 if (IS_ERR(priv->fdvfs)) in mtk_cpufreq_hw_mt8196_init() 76 return dev_err_probe(priv->dev, PTR_ERR(priv->fdvfs), in mtk_cpufreq_hw_mt8196_init() 103 policy = cpufreq_cpu_get_raw(cpu_dev->id); in mtk_cpufreq_get_cpu_power() 105 return -EINVAL; in mtk_cpufreq_get_cpu_power() 107 data = policy->driver_data; in mtk_cpufreq_get_cpu_power() 109 for (i = 0; i < data->nr_opp; i++) { in mtk_cpufreq_get_cpu_power() 110 if (data->table[i].frequency < *KHz) in mtk_cpufreq_get_cpu_power() 113 i--; in mtk_cpufreq_get_cpu_power() [all …]
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/linux/arch/arm/mach-omap2/ |
H A D | omap_opp_data.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/ 25 * struct omap_opp_def - OMAP OPP Definition 26 * @hwmod_name: Name of the hwmod for this domain 27 * @freq: Frequency in hertz corresponding to this OPP 29 * @default_available: True/false - is this OPP available by default 32 * pairs that the device will support per voltage domain. This is called 35 * domain, you can have a set of {frequency, voltage} pairs and this is denoted 39 * which belongs to a voltage domain may define their own set of OPPs on top 40 * of this - but this is handled by the appropriate driver. [all …]
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/linux/Documentation/power/ |
H A D | opp.rst | 5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated 20 ------------------------------------------------- 22 Complex SoCs of today consists of a multiple sub-modules working in conjunction. 25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some 30 the device will support per domain are called Operating Performance Points or 41 - {300000000, 1000000} 42 - {800000000, 1200000} 43 - {1000000000, 1300000} 46 ---------------------------------------- 57 (users) -> registers a set of default OPPs -> (library) [all …]
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H A D | energy-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0 8 ----------- 12 subsystems willing to use that information to make energy-aware decisions. 18 each and every client subsystem to re-implement support for each and every 23 The power values might be expressed in micro-Watts or in an 'abstract scale'. 26 can be found in the Energy-Aware Scheduler documentation 27 Documentation/scheduler/sched-energy.rst. For some subsystems like thermal or 30 thus the real micro-Watts might be needed. An example of these requirements can 32 Documentation/driver-api/thermal/power_allocator.rst. 36 an 'abstract scale' deriving real energy in micro-Joules would not be possible. [all …]
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/linux/net/wireless/ |
H A D | reg.h | 7 * Copyright 2008-2011 Luis R. Rodriguez <mcgrof@qca.qualcomm.com> 40 * regulatory_hint_indoor - hint operation in indoor env. or not 48 * regulatory_netlink_notify - notify on released netlink socket 68 * regulatory_hint_found_beacon - hints a beacon was found on a channel 76 * world roaming -- when we do not know our current location. This is 78 * 1-11 are already enabled by the world regulatory domain; and on 79 * non-radar 5 GHz channels. 83 * set the wiphy->disable_beacon_hints to true. 90 * regulatory_hint_country_ie - hints a country IE as a regulatory domain 116 * regulatory_hint_disconnect - informs all devices have been disconnected [all …]
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H A D | reg.c | 2 * Copyright 2002-2005, Instant802 Networks, Inc. 3 * Copyright 2005-2006, Devicescape Software, Inc. 5 * Copyright 2008-2011 Luis R. Rodriguez <mcgrof@qca.qualcomm.com> 6 * Copyright 2013-2014 Intel Mobile Communications GmbH 8 * Copyright (C) 2018 - 2025 Intel Corporation 28 * determine which regulatory domain it should be operating under, then 29 * looking up the allowable channels in a driver-local table and finally 42 * Note: When number of rules --> infinity we will not be able to 65 #include "rdev-op 880 __regdb_query_wmm(const struct fwdb_header * db,const struct fwdb_country * country,int freq,struct ieee80211_reg_rule * rrule) __regdb_query_wmm() argument 905 reg_query_regdb_wmm(char * alpha2,int freq,struct ieee80211_reg_rule * rule) reg_query_regdb_wmm() argument 3648 freq_is_chan_12_13_14(u32 freq) freq_is_chan_12_13_14() argument 4152 cfg80211_get_unii(int freq) cfg80211_get_unii() argument [all...] |
/linux/drivers/pmdomain/qcom/ |
H A D | cpr.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 27 #include <linux/nvmem-consumer.h> 29 /* Register Offsets for RB-CPR and Bit Definitions */ 125 #define FUSE_REVISION_UNKNOWN (-1) 163 unsigned long freq; member 221 unsigned long freq; member 254 return !drv->loop_disabled; in cpr_is_allowed() 259 writel_relaxed(value, drv->base + offset); in cpr_write() 264 return readl_relaxed(drv->base + offset); in cpr_read() [all …]
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/linux/drivers/irqchip/ |
H A D | irq-bcm2836.c | 1 // SPDX-License-Identifier: GPL-2.0+ 14 #include <linux/irqchip/irq-bcm2836.h> 19 struct irq_domain *domain; member 46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq() 53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq() 58 .name = "bcm2836-timer", 75 .name = "bcm2836-pmu", 90 .name = "bcm2836-gpu", 101 .name = "bcm2836-dummy", 128 return -EINVAL; in bcm2836_map() [all …]
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/linux/tools/testing/selftests/net/forwarding/ |
H A D | tsn_lib.sh | 2 # SPDX-License-Identifier: GPL-2.0 3 # Copyright 2021-2022 NXP 5 tc_testing_scripts_dir=$(dirname $0)/../../tc-testing/scripts 15 # https://github.com/vladimiroltean/tsn-scripts 16 # WARNING: isochron versions pre-1.0 are unstable, 31 if ! [ -z "${uds_address}" ]; then 32 extra_args="${extra_args} -z ${uds_address}" 37 chrt -f 10 phc2sys -m \ 38 -a -rr \ 39 --step_threshold 0.00002 \ [all …]
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/linux/drivers/staging/rtl8723bs/os_dep/ |
H A D | wifi_regd.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright(c) 2009-2010 Realtek Corporation. 13 * REG_RULE(freq start, freq end, bandwidth, max gain, eirp, reg_flags) 21 /* 2G chan 01 - chan 11 */ 23 REG_RULE(2412 - 10, 2462 + 10, 40, 0, 20, 0) 27 * by case basis by regulatory domain 30 /* 2G chan 12 - chan 13, PASSIV SCAN */ 32 REG_RULE(2467 - 10, 2472 + 10, 40, 0, 20, \ 47 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; in _rtw_reg_apply_flags() 48 struct rt_channel_info *channel_set = pmlmeext->channel_set; in _rtw_reg_apply_flags() [all …]
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