Lines Matching +full:freq +full:- +full:domain
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
26 xo_board: xo-board {
27 compatible = "fixed-clock";
28 clock-frequency = <76800000>;
29 #clock-cells = <0>;
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
34 clock-frequency = <32764>;
35 #clock-cells = <0>;
38 bi_tcxo_div2: bi-tcxo-div2-clk {
39 #clock-cells = <0>;
40 compatible = "fixed-factor-clock";
42 clock-mult = <1>;
43 clock-div = <2>;
48 #address-cells = <2>;
49 #size-cells = <0>;
53 compatible = "arm,cortex-a55";
56 enable-method = "psci";
57 next-level-cache = <&l2_0>;
58 power-domains = <&cpu_pd0>;
59 power-domain-names = "psci";
60 qcom,freq-domain = <&cpufreq_hw 0>;
61 #cooling-cells = <2>;
63 l2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
69 l3_0: l3-cache {
71 cache-level = <3>;
72 cache-unified;
79 compatible = "arm,cortex-a55";
82 enable-method = "psci";
83 next-level-cache = <&l2_100>;
84 power-domains = <&cpu_pd0>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>;
89 l2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&l3_0>;
99 compatible = "arm,cortex-a55";
102 enable-method = "psci";
103 next-level-cache = <&l2_200>;
104 power-domains = <&cpu_pd0>;
105 power-domain-names = "psci";
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 #cooling-cells = <2>;
109 l2_200: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&l3_0>;
119 compatible = "arm,cortex-a55";
122 enable-method = "psci";
123 next-level-cache = <&l2_300>;
124 power-domains = <&cpu_pd0>;
125 power-domain-names = "psci";
126 qcom,freq-domain = <&cpufreq_hw 0>;
127 #cooling-cells = <2>;
129 l2_300: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
139 compatible = "arm,cortex-a55";
142 enable-method = "psci";
143 next-level-cache = <&l2_400>;
144 power-domains = <&cpu_pd0>;
145 power-domain-names = "psci";
146 qcom,freq-domain = <&cpufreq_hw 0>;
147 #cooling-cells = <2>;
149 l2_400: l2-cache {
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&l3_0>;
159 compatible = "arm,cortex-a55";
162 enable-method = "psci";
163 next-level-cache = <&l2_500>;
164 power-domains = <&cpu_pd0>;
165 power-domain-names = "psci";
166 qcom,freq-domain = <&cpufreq_hw 0>;
167 #cooling-cells = <2>;
169 l2_500: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&l3_0>;
179 compatible = "arm,cortex-a78";
182 enable-method = "psci";
183 next-level-cache = <&l2_600>;
184 power-domains = <&cpu_pd0>;
185 power-domain-names = "psci";
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 #cooling-cells = <2>;
189 l2_600: l2-cache {
191 cache-level = <2>;
192 cache-unified;
193 next-level-cache = <&l3_0>;
199 compatible = "arm,cortex-a78";
202 enable-method = "psci";
203 next-level-cache = <&l2_700>;
204 power-domains = <&cpu_pd0>;
205 power-domain-names = "psci";
206 qcom,freq-domain = <&cpufreq_hw 1>;
207 #cooling-cells = <2>;
209 l2_700: l2-cache {
211 cache-level = <2>;
212 cache-unified;
213 next-level-cache = <&l3_0>;
217 cpu-map {
253 idle-states {
254 entry-method = "psci";
256 little_cpu_sleep_0: cpu-sleep-0-0 {
257 compatible = "arm,idle-state";
258 arm,psci-suspend-param = <0x40000004>;
259 entry-latency-us = <800>;
260 exit-latency-us = <750>;
261 min-residency-us = <4090>;
262 local-timer-stop;
265 big_cpu_sleep_0: cpu-sleep-1-0 {
266 compatible = "arm,idle-state";
267 arm,psci-suspend-param = <0x40000004>;
268 entry-latency-us = <600>;
269 exit-latency-us = <1550>;
270 min-residency-us = <4791>;
271 local-timer-stop;
275 domain-idle-states {
276 cluster_sleep_0: cluster-sleep-0 {
277 compatible = "domain-idle-state";
278 arm,psci-suspend-param = <0x41000044>;
279 entry-latency-us = <1050>;
280 exit-latency-us = <2500>;
281 min-residency-us = <5309>;
284 cluster_sleep_1: cluster-sleep-1 {
285 compatible = "domain-idle-state";
286 arm,psci-suspend-param = <0x41003344>;
287 entry-latency-us = <1561>;
288 exit-latency-us = <2801>;
289 min-residency-us = <8550>;
300 pmu-a55 {
301 compatible = "arm,cortex-a55-pmu";
305 pmu-a78 {
306 compatible = "arm,cortex-a78-pmu";
311 compatible = "arm,psci-1.0";
314 cpu_pd0: power-domain-cpu0 {
315 #power-domain-cells = <0>;
316 power-domains = <&cluster_pd>;
317 domain-idle-states = <&little_cpu_sleep_0>;
320 cpu_pd1: power-domain-cpu1 {
321 #power-domain-cells = <0>;
322 power-domains = <&cluster_pd>;
323 domain-idle-states = <&little_cpu_sleep_0>;
326 cpu_pd2: power-domain-cpu2 {
327 #power-domain-cells = <0>;
328 power-domains = <&cluster_pd>;
329 domain-idle-states = <&little_cpu_sleep_0>;
332 cpu_pd3: power-domain-cpu3 {
333 #power-domain-cells = <0>;
334 power-domains = <&cluster_pd>;
335 domain-idle-states = <&little_cpu_sleep_0>;
338 cpu_pd4: power-domain-cpu4 {
339 #power-domain-cells = <0>;
340 power-domains = <&cluster_pd>;
341 domain-idle-states = <&big_cpu_sleep_0>;
344 cpu_pd5: power-domain-cpu5 {
345 #power-domain-cells = <0>;
346 power-domains = <&cluster_pd>;
347 domain-idle-states = <&big_cpu_sleep_0>;
350 cpu_pd6: power-domain-cpu6 {
351 #power-domain-cells = <0>;
352 power-domains = <&cluster_pd>;
353 domain-idle-states = <&big_cpu_sleep_0>;
356 cpu_pd7: power-domain-cpu7 {
357 #power-domain-cells = <0>;
358 power-domains = <&cluster_pd>;
359 domain-idle-states = <&big_cpu_sleep_0>;
362 cluster_pd: power-domain-cpu-cluster0 {
363 #power-domain-cells = <0>;
364 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
368 reserved_memory: reserved-memory {
369 #address-cells = <2>;
370 #size-cells = <2>;
373 aop_cmd_db_mem: cmd-db@80860000 {
374 compatible = "qcom,cmd-db";
376 no-map;
381 #address-cells = <2>;
382 #size-cells = <2>;
384 dma-ranges = <0 0 0 0 0x10 0>;
385 compatible = "simple-bus";
387 gcc: clock-controller@100000 {
388 compatible = "qcom,sm4450-gcc";
390 #clock-cells = <1>;
391 #reset-cells = <1>;
392 #power-domain-cells = <1>;
402 compatible = "qcom,geni-se-qup";
407 clock-names = "m-ahb", "s-ahb";
408 #address-cells = <2>;
409 #size-cells = <2>;
413 compatible = "qcom,geni-debug-uart";
416 clock-names = "se";
418 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
419 pinctrl-names = "default";
425 compatible = "qcom,tcsr-mutex";
427 #hwlock-cells = <1>;
430 gpucc: clock-controller@3d90000 {
431 compatible = "qcom,sm4450-gpucc";
436 #clock-cells = <1>;
437 #reset-cells = <1>;
438 #power-domain-cells = <1>;
441 camcc: clock-controller@ade0000 {
442 compatible = "qcom,sm4450-camcc";
446 #clock-cells = <1>;
447 #reset-cells = <1>;
448 #power-domain-cells = <1>;
451 dispcc: clock-controller@af00000 {
452 compatible = "qcom,sm4450-dispcc";
460 #clock-cells = <1>;
461 #reset-cells = <1>;
462 #power-domain-cells = <1>;
465 pdc: interrupt-controller@b220000 {
466 compatible = "qcom,sm4450-pdc", "qcom,pdc";
468 qcom,pdc-ranges = <0 480 94>, <94 494 31>,
470 #interrupt-cells = <2>;
471 interrupt-parent = <&intc>;
472 interrupt-controller;
476 compatible = "qcom,sm4450-tlmm";
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 gpio-ranges = <&tlmm 0 0 137>;
484 wakeup-parent = <&pdc>;
486 qup_uart7_rx: qup-uart7-rx-state {
489 drive-strength = <2>;
490 bias-disable;
493 qup_uart7_tx: qup-uart7-tx-state {
496 drive-strength = <2>;
497 bias-disable;
501 intc: interrupt-controller@17200000 {
502 compatible = "arm,gic-v3";
506 #interrupt-cells = <3>;
507 interrupt-controller;
508 #redistributor-regions = <1>;
509 redistributor-stride = <0x0 0x20000>;
513 compatible = "arm,armv7-timer-mem";
516 #address-cells = <1>;
517 #size-cells = <1>;
522 frame-number = <0>;
529 frame-number = <1>;
536 frame-number = <2>;
543 frame-number = <3>;
550 frame-number = <4>;
557 frame-number = <5>;
564 frame-number = <6>;
571 compatible = "qcom,rpmh-rsc";
575 reg-names = "drv-0", "drv-1", "drv-2";
580 qcom,tcs-offset = <0xd00>;
581 qcom,drv-id = <2>;
582 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
584 power-domains = <&cluster_pd>;
586 apps_bcm_voter: bcm-voter {
587 compatible = "qcom,bcm-voter";
590 rpmhcc: clock-controller {
591 compatible = "qcom,sm4450-rpmh-clk";
592 #clock-cells = <1>;
594 clock-names = "xo";
597 rpmhpd: power-controller {
598 compatible = "qcom,sm4450-rpmhpd";
599 #power-domain-cells = <1>;
600 operating-points-v2 = <&rpmhpd_opp_table>;
602 rpmhpd_opp_table: opp-table {
603 compatible = "operating-points-v2";
605 rpmhpd_opp_ret: opp-16 {
606 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
609 rpmhpd_opp_min_svs: opp-48 {
610 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
613 rpmhpd_opp_low_svs_d1: opp-56 {
614 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
617 rpmhpd_opp_low_svs: opp-64 {
618 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
621 rpmhpd_opp_low_svs_l1: opp-80 {
622 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
625 rpmhpd_opp_low_svs_l2: opp-96 {
626 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
629 rpmhpd_opp_svs: opp-128 {
630 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
633 rpmhpd_opp_svs_l1: opp-192 {
634 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
637 rpmhpd_opp_svs_l2: opp-224 {
638 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
641 rpmhpd_opp_nom: opp-256 {
642 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
645 rpmhpd_opp_nom_l1: opp-320 {
646 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
649 rpmhpd_opp_nom_l2: opp-336 {
650 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
653 rpmhpd_opp_turbo: opp-384 {
654 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
657 rpmhpd_opp_turbo_l1: opp-416 {
658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
665 compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
668 reg-names = "freq-domain0", "freq-domain1";
670 clock-names = "xo", "alternate";
673 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
674 #freq-domain-cells = <1>;
675 #clock-cells = <1>;
680 compatible = "arm,armv8-timer";