Lines Matching +full:freq +full:- +full:domain
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
50 * Mutex to synchronize between de-init sequence and re-starting LMh
80 dev = get_cpu_device(policy->cpu);
82 return -ENODEV;
106 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
116 struct qcom_cpufreq_data *data = policy->driver_data;
118 unsigned long freq = policy->freq_table[index].frequency;
121 writel_relaxed(index, data->base + soc_data->reg_perf_state);
123 if (data->per_core_dcvs)
124 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
125 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
128 qcom_cpufreq_set_bw(policy, freq);
137 if (qcom_cpufreq.soc_data->reg_current_vote)
138 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_vote) & 0x3ff;
140 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_state) & 0xff;
155 data = policy->driver_data;
158 index = readl_relaxed(data->base + soc_data->reg_perf_state);
159 index = min(index, LUT_MAX_ENTRIES - 1);
161 return policy->freq_table[index].frequency;
171 data = policy->driver_data;
173 if (data->throttle_irq >= 0)
187 struct qcom_cpufreq_data *data = policy->driver_data;
192 index = policy->cached_resolved_idx;
193 writel_relaxed(index, data->base + soc_data->reg_perf_state);
195 if (data->per_core_dcvs)
196 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
197 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
199 return policy->freq_table[index].frequency;
205 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
211 struct qcom_cpufreq_data *drv_data = policy->driver_data;
216 return -ENOMEM;
220 /* Disable all opps and cross-validate against LUT later */
230 } else if (ret != -ENODEV) {
235 policy->fast_switch_possible = true;
240 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
241 i * soc_data->lut_row_size);
246 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
247 i * soc_data->lut_row_size);
251 freq = xo_rate * lval / 1000;
253 freq = cpu_hw_rate / 1000;
255 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
256 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
257 table[i].frequency = freq;
258 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
259 freq, core_count);
261 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
273 if (i > 0 && prev_freq == freq) {
274 struct cpufreq_frequency_table *prev = &table[i - 1];
280 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
282 prev->frequency = prev_freq;
283 prev->flags = CPUFREQ_BOOST_FREQ;
285 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
286 freq);
293 prev_freq = freq;
297 policy->freq_table = table;
298 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
314 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
315 "#freq-domain-cells", 0,
328 struct cpufreq_policy *policy = data->policy;
329 int cpu = cpumask_first(policy->related_cpus);
341 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
353 arch_update_hw_pressure(policy->related_cpus, throttled_freq);
359 mutex_lock(&data->throttle_lock);
360 if (data->cancel_throttle)
368 enable_irq(data->throttle_irq);
370 mod_delayed_work(system_highpri_wq, &data->throttle_work,
374 mutex_unlock(&data->throttle_lock);
390 disable_irq_nosync(c_data->throttle_irq);
391 schedule_delayed_work(&c_data->throttle_work, 0);
393 if (qcom_cpufreq.soc_data->reg_intr_clr)
395 c_data->base + qcom_cpufreq.soc_data->reg_intr_clr);
422 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
423 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
430 struct qcom_cpufreq_data *data = policy->driver_data;
438 data->throttle_irq = platform_get_irq_optional(pdev, index);
439 if (data->throttle_irq == -ENXIO)
441 if (data->throttle_irq < 0)
442 return data->throttle_irq;
444 data->cancel_throttle = false;
446 mutex_init(&data->throttle_lock);
447 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
449 snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
450 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
451 IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
453 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
457 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
459 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
460 data->irq_name, data->throttle_irq);
467 struct qcom_cpufreq_data *data = policy->driver_data;
471 if (data->throttle_irq <= 0)
474 mutex_lock(&data->throttle_lock);
475 data->cancel_throttle = false;
476 mutex_unlock(&data->throttle_lock);
478 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
480 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
481 data->irq_name, data->throttle_irq);
488 struct qcom_cpufreq_data *data = policy->driver_data;
490 if (data->throttle_irq <= 0)
493 mutex_lock(&data->throttle_lock);
494 data->cancel_throttle = true;
495 mutex_unlock(&data->throttle_lock);
497 cancel_delayed_work_sync(&data->throttle_work);
498 irq_set_affinity_and_hint(data->throttle_irq, NULL);
499 disable_irq_nosync(data->throttle_irq);
506 if (data->throttle_irq <= 0)
509 free_irq(data->throttle_irq, data);
515 struct device *dev = &pdev->dev;
522 cpu_dev = get_cpu_device(policy->cpu);
525 policy->cpu);
526 return -ENODEV;
529 cpu_np = of_cpu_device_node_get(policy->cpu);
531 return -EINVAL;
533 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
534 "#freq-domain-cells", 0, &args);
543 if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) {
544 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
545 return -ENODEV;
548 if (readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_dcvs_ctrl) & 0x1)
549 data->per_core_dcvs = true;
551 qcom_get_related_cpus(index, policy->cpus);
553 policy->driver_data = data;
554 policy->dvfs_possible_from_any_cpu = true;
555 data->policy = policy;
559 dev_err(dev, "Domain-%d failed to read LUT\n", index);
566 return -ENODEV;
574 struct device *cpu_dev = get_cpu_device(policy->cpu);
575 struct qcom_cpufreq_data *data = policy->driver_data;
578 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
580 kfree(policy->freq_table);
586 struct qcom_cpufreq_data *data = policy->driver_data;
588 if (data->throttle_irq >= 0)
589 enable_irq(data->throttle_irq);
605 .name = "qcom-cpufreq-hw",
614 return __qcom_cpufreq_hw_get(data->policy) * HZ_PER_KHZ;
624 req->rate = qcom_cpufreq_hw_recalc_rate(hw, 0);
637 struct device *dev = &pdev->dev;
661 return -EPROBE_DEFER;
674 return -ENOMEM;
678 return -ENODEV;
682 return -ENOMEM;
684 clk_data->num = num_domains;
697 data->base = base;
699 /* Register CPU clock for each frequency domain */
702 return -ENOMEM;
706 data->cpu_clk.init = &clk_init;
708 ret = devm_clk_hw_register(dev, &data->cpu_clk);
715 clk_data->hws[i] = &data->cpu_clk;
743 .name = "qcom-cpufreq-hw",