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Searched +full:fpga +full:- +full:slave +full:- +full:serial (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,fpga-slave-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
14 over what is referred to as slave serial interface.The slave serial link is
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
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H A Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
14 have Slave Serial Peripheral Interface. Only full reconfiguration is
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
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/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define PA_BCR 0xa4000000 /* FPGA */
11 #define PA_SDPOW (-1)
38 #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
40 #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
42 #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
47 #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
49 #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
50 #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
52 #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
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/linux/drivers/fpga/
H A Dmachxo2-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Lattice MachXO2 Slave SPI Driver
5 * Manage Lattice FPGA firmware that is loaded over SPI using
6 * the slave serial configuration interface.
12 #include <linux/fpga/fpga-mgr.h>
18 /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
29 * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
30 * Sheet' sysCONFIG Port Timing Specifications (3-36)
112 pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n", in dump_status_reg()
129 return -EBUSY; in wait_until_not_busy()
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/linux/Documentation/userspace-api/media/
H A Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
31 consists of one or more related samples while on serial buses the data
57 FPGA
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
68 :term:`SoC` or :term:`FPGA`.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
83 serial computer bus used to control some hardware components
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/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
48 Interconnect. In case of any APB protocol collisions, slave device
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
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/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h1 /* SPDX-License-Identifier: GPL-2.0 */
71 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
77 #define PWRCR_SCIEN BIT(2) /* Serial port enable */
131 /* arch/sh/boards/mach-sdk7786/fpga.c */
135 /* arch/sh/boards/mach-sdk7786/nmi.c */
142 * when the FPGA is in I2C slave mode.
/linux/drivers/tty/serial/8250/
H A D8250_exar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
5 * Based on drivers/tty/serial/8250/8250_pci.c,
114 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
115 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
133 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
150 * ---- ---- --------
154 * 3 - <reserved>
158 * 7 - <reserved>
161 * 10 - Red LED
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/linux/include/sound/
H A Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ----
1711 unsigned int serial; /* serial number */ global() member
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/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
106 3 char Pseudo-TTY slaves
107 0 = /dev/ttyp0 First PTY slave
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/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/sound/pci/rme9652/
H A Dhdspm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Modified 2006-06-01 for AES32 support by Remy Bruno
12 * Modified 2009-04-13 for proper metering by Florian Faber
15 * Modified 2009-0
1067 unsigned int serial; global() member
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/drivers/ptp/
H A Dptp_ocp.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
24 #include <linux/nvmem-consumer.h>
376 u8 serial[OCP_SERIAL_LEN]; member
441 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
446 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
452 { EEPROM_ENTRY(0x200 + 0x63, serial) },
457 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
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