Lines Matching +full:fpga +full:- +full:slave +full:- +full:serial
1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define PA_BCR 0xa4000000 /* FPGA */
11 #define PA_SDPOW (-1)
38 #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
40 #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
42 #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
47 #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
49 #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
50 #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
52 #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
54 #define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
59 #define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
61 #define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
62 #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
63 #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
64 #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
65 #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
66 #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
67 #define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
75 #define PA_POFF (-1)
77 #define PA_BCR 0xa5000000 /* FPGA */
105 #define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
107 #define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
109 #define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
114 #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
115 #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
116 #define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
117 #define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
118 #define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
119 #define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
131 #define PA_BCR 0xa4000000 /* FPGA */
132 #define PA_SDPOW (-1)