| /linux/drivers/fpga/ |
| H A D | ts73xx-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
35 static int ts73xx_fpga_write_init(struct fpga_manager *mgr, in ts73xx_fpga_write_init() argument
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
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| H A D | socfpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera SOCFPGA
5 * Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 "FPGA-1.5V",
99 "FPGA-1.1V",
100 "FPGA-2.5V",
136 return readl(priv->fpga_base_addr + reg_offset); in socfpga_fpga_readl()
142 writel(value, priv->fpga_base_addr + reg_offset); in socfpga_fpga_writel()
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| H A D | zynqmp-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
28 static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, in zynqmp_fpga_ops_write_init() argument
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
40 static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, in zynqmp_fpga_ops_write() argument
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
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| H A D | microchip-spi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip Polarfire FPGA programming over slave SPI interface.
8 #include <linux/fpga/fpga-mgr.h>
59 .tx_buf = &priv->tx, in mpf_read_status()
60 .rx_buf = &priv->rx, in mpf_read_status()
64 .tx_buf = &priv->tx, in mpf_read_status()
65 .rx_buf = &priv->rx, in mpf_read_status()
72 priv->tx = MPF_SPI_READ_STATUS; in mpf_read_status()
74 ret = spi_sync_transfer(priv->spi, xfers, 2); in mpf_read_status()
78 status = priv->rx; in mpf_read_status()
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| H A D | zynq-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
6 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
29 /* FPGA Software Reset Control */
61 /* Signal to reset FPGA */
78 /* FPGA init status */
88 /* FPGA programmed */
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
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| H A D | dfl-fme-mgr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
22 #include <linux/io-64-nonatomic-lo-hi.h>
23 #include <linux/fpga/fpga-mgr.h>
25 #include "dfl-fme-pr.h"
52 /* PR data from the raw-binary file. */
107 static int fme_mgr_write_init(struct fpga_manager *mgr, in fme_mgr_write_init() argument
111 struct device *dev = &mgr->dev; in fme_mgr_write_init()
112 struct fme_mgr_priv *priv = mgr->priv; in fme_mgr_write_init()
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| H A D | machxo2-spi.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Manage Lattice FPGA firmware that is loaded over SPI using
12 #include <linux/fpga/fpga-mgr.h>
18 /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
30 * Sheet' sysCONFIG Port Timing Specifications (3-36)
112 pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n", in dump_status_reg()
129 return -EBUSY; in wait_until_not_busy()
135 static int machxo2_cleanup(struct fpga_manager *mgr) in machxo2_cleanup() argument
137 struct spi_device *spi = mgr->priv; in machxo2_cleanup()
169 dev_err(&mgr->dev, "Cleanup failed\n"); in machxo2_cleanup()
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| H A D | altera-pr-ip-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Intel Corporation
7 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
11 #include <linux/fpga/altera-pr-ip-core.h>
12 #include <linux/fpga/fpga-mgr.h>
32 static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr) in alt_pr_fpga_state() argument
34 struct alt_pr_priv *priv = mgr->priv; in alt_pr_fpga_state()
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
72 dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n", in alt_pr_fpga_state()
77 static int alt_pr_fpga_write_init(struct fpga_manager *mgr, in alt_pr_fpga_write_init() argument
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| H A D | lattice-sysconfig.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Lattice FPGA sysCONFIG interface functions independent of port type.
7 #include <linux/fpga/fpga-mgr.h>
11 #include "lattice-sysconfig.h"
16 return priv->command_transfer(priv, buf, buf_len, NULL, 0); in sysconfig_cmd_write()
22 return priv->command_transfer(priv, tx_buf, tx_len, rx_buf, rx_len); in sysconfig_cmd_read()
91 struct gpio_desc *program = priv->program; in sysconfig_gpio_refresh()
92 struct gpio_desc *init = priv->init; in sysconfig_gpio_refresh()
93 struct gpio_desc *done = priv->done; in sysconfig_gpio_refresh()
128 struct gpio_desc *program = priv->program; in sysconfig_refresh()
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| H A D | dfl-fme-pr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 * struct dfl_fme_region - FME fpga region data structure
26 * @region: platform device of the FPGA region.
37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
39 * @mgr: platform device of the FPGA manager.
40 * @br: platform device of the FPGA bridge.
44 struct platform_device *mgr; member
50 * struct dfl_fme_bridge - FME fpga bridge data structure
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| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | intel,stratix10-soc-fpga-mgr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Stratix10 SoC FPGA Manager
10 - Mahesh Rao <mahesh.rao@altera.com>
11 - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
12 - Niravkumar L Rabara <nirav.rabara@altera.com>
15 The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard
17 SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric
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| H A D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
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| H A D | microchip,mpf-spi-fpga-mgr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Polarfire FPGA manager.
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
26 - compatible
27 - reg
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| H A D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
24 fpga_mgr_spi: fpga-mgr@0 {
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| H A D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
4 - compatible : should contain "altr,socfpga-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
13 compatible = "altr,socfpga-fpga-mgr";
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| H A D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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| H A D | lattice-ice40-fpga-mgr.txt | 1 Lattice iCE40 FPGA Manager
4 - compatible: Should contain "lattice,ice40-fpga-mgr"
5 - reg: SPI chip select
6 - spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
7 - cdone-gpios: GPIO input connected to CDONE pin
8 - reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
10 FPGA will enter Master SPI mode and drive SCK with a
15 fpga: fpga@0 {
16 compatible = "lattice,ice40-fpga-mgr";
18 spi-max-frequency = <1000000>;
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| H A D | altr,socfpga-hps2fpga-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA/HPS Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
18 - altr,socfpga-lwhps2fpga-bridge
19 - altr,socfpga-hps2fpga-bridge
20 - altr,socfpga-fpga2hps-bridge
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| /linux/Documentation/driver-api/fpga/ |
| H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
19 * re-enable the bridges
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| H A D | index.rst | 2 FPGA Subsystem
11 fpga-mgr
12 fpga-bridge
13 fpga-region
14 fpga-programming
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| H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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| /linux/drivers/fpga/tests/ |
| H A D | fpga-region-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
28 struct fpga_manager *mgr; member
51 static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) in op_write() argument
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
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| H A D | fpga-mgr-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Manager
12 #include <linux/fpga/fpga-mgr.h>
42 struct fpga_manager *mgr; member
58 * init_test_buffer() - Allocate and initialize a test image in a buffer.
74 memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE); in init_test_buffer()
81 * since, in this case, it is a failure of the FPGA manager itself, not this
84 static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info, in op_parse_header() argument
87 struct mgr_stats *stats = mgr->priv; in op_parse_header()
90 stats->op_parse_header_state = mgr->state; in op_parse_header()
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for KUnit test suites for the FPGA subsystem
6 obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o
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| /linux/Documentation/devicetree/bindings/firmware/ |
| H A D | intel,stratix10-svc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
11 - Mahesh Rao <mahesh.rao@altera.com>
14 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
15 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
18 configuration data from that location and perform the FPGA configuration.
28 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
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