1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2016-2017 Intel Corporation
7  * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
11 #include <linux/fpga/altera-pr-ip-core.h>
12 #include <linux/fpga/fpga-mgr.h>
32 static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)  in alt_pr_fpga_state()  argument
34 	struct alt_pr_priv *priv = mgr->priv;  in alt_pr_fpga_state()
39 	val = readl(priv->reg_base + ALT_PR_CSR_OFST);  in alt_pr_fpga_state()
72 	dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",  in alt_pr_fpga_state()
77 static int alt_pr_fpga_write_init(struct fpga_manager *mgr,  in alt_pr_fpga_write_init()  argument
81 	struct alt_pr_priv *priv = mgr->priv;  in alt_pr_fpga_write_init()
84 	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {  in alt_pr_fpga_write_init()
85 		dev_err(&mgr->dev, "%s Partial Reconfiguration flag not set\n",  in alt_pr_fpga_write_init()
87 		return -EINVAL;  in alt_pr_fpga_write_init()
90 	val = readl(priv->reg_base + ALT_PR_CSR_OFST);  in alt_pr_fpga_write_init()
93 		dev_err(&mgr->dev,  in alt_pr_fpga_write_init()
96 		return -EINVAL;  in alt_pr_fpga_write_init()
99 	writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);  in alt_pr_fpga_write_init()
104 static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,  in alt_pr_fpga_write()  argument
107 	struct alt_pr_priv *priv = mgr->priv;  in alt_pr_fpga_write()
112 		return -EINVAL;  in alt_pr_fpga_write()
114 	/* Write out the complete 32-bit chunks */  in alt_pr_fpga_write()
116 		writel(buffer_32[i++], priv->reg_base);  in alt_pr_fpga_write()
117 		count -= sizeof(u32);  in alt_pr_fpga_write()
120 	/* Write out remaining non 32-bit chunks */  in alt_pr_fpga_write()
123 		writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);  in alt_pr_fpga_write()
126 		writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);  in alt_pr_fpga_write()
129 		writel(buffer_32[i++] & 0x000000ff, priv->reg_base);  in alt_pr_fpga_write()
135 		return -EFAULT;  in alt_pr_fpga_write()
138 	if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)  in alt_pr_fpga_write()
139 		return -EIO;  in alt_pr_fpga_write()
144 static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,  in alt_pr_fpga_write_complete()  argument
150 		switch (alt_pr_fpga_state(mgr)) {  in alt_pr_fpga_write_complete()
152 			return -EIO;  in alt_pr_fpga_write_complete()
155 			dev_info(&mgr->dev,  in alt_pr_fpga_write_complete()
163 	} while (info->config_complete_timeout_us > i++);  in alt_pr_fpga_write_complete()
165 	dev_err(&mgr->dev, "timed out waiting for write to complete\n");  in alt_pr_fpga_write_complete()
166 	return -ETIMEDOUT;  in alt_pr_fpga_write_complete()
179 	struct fpga_manager *mgr;  in alt_pr_register()  local
184 		return -ENOMEM;  in alt_pr_register()
186 	priv->reg_base = reg_base;  in alt_pr_register()
188 	val = readl(priv->reg_base + ALT_PR_CSR_OFST);  in alt_pr_register()
194 	mgr = devm_fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);  in alt_pr_register()
195 	return PTR_ERR_OR_ZERO(mgr);  in alt_pr_register()