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/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dintel,stratix10-soc-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Stratix10 SoC FPGA Manager
10 - Mahesh Rao <mahesh.rao@altera.com>
11 - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
12 - Niravkumar L Rabara <nirav.rabara@altera.com>
15 The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard
17 SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric
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H A Dintel-stratix10-soc-fpga-mgr.txt1 Intel Stratix10 SoC FPGA Manager
7 - compatible : should contain "intel,stratix10-soc-fpga-mgr" or
8 "intel,agilex-soc-fpga-mgr"
14 fpga_mgr: fpga-mgr {
15 compatible = "intel,stratix10-soc-fpga-mgr";
H A Daltera-socfpga-a10-fpga-mgr.txt1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
H A Dfpga-region.txt1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Region
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H A Dmicrochip,mpf-spi-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Polarfire FPGA manager.
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
26 - compatible
27 - reg
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H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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H A Dlattice-machxo2-spi.txt1 Lattice MachXO2 Slave SPI FPGA Manager
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
24 fpga_mgr_spi: fpga-mgr@0 {
[all …]
H A Daltera-socfpga-fpga-mgr.txt1 Altera SOCFPGA FPGA Manager
4 - compatible : should contain "altr,socfpga-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
13 compatible = "altr,socfpga-fpga-mgr";
H A Dlattice-ice40-fpga-mgr.txt1 Lattice iCE40 FPGA Manager
4 - compatible: Should contain "lattice,ice40-fpga-mgr"
5 - reg: SPI chip select
6 - spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
7 - cdone-gpios: GPIO input connected to CDONE pin
8 - reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
10 FPGA will enter Master SPI mode and drive SCK with a
15 fpga: fpga@0 {
16 compatible = "lattice,ice40-fpga-mgr";
18 spi-max-frequency = <1000000>;
[all …]
H A Dxilinx-slave-serial.txt1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
9 - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
10 - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
14 - compatible: should contain "xlnx,fpga-slave-serial"
15 - reg: spi chip select of the FPGA
16 - prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
17 - done-gpios: config status pin (referred to as DONE in the manual)
20 - init-b-gpios: initialization status and configuration error pin
[all …]
H A Dxlnx,zynqmp-pcap-fpga.txt1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
8 Example for full FPGA configuration:
10 fpga-region0 {
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
13 #address-cells = <0x1>;
14 #size-cells = <0x1>;
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
[all …]
H A Dxlnx,fpga-selectmap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SelectMAP FPGA interface
10 - Charles Perry <charles.perry@savoirfairelinux.com>
22 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
27 - xlnx,fpga-xc7s-selectmap
28 - xlnx,fpga-xc7a-selectmap
29 - xlnx,fpga-xc7k-selectmap
[all …]
H A Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
28 program-gpios:
[all …]
H A Dxlnx,fpga-slave-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
29 - xlnx,fpga-slave-serial
[all …]
H A Dxilinx-zynq-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq FPGA Manager
10 - Michal Simek <michal.simek@amd.com>
14 const: xlnx,zynq-devcfg-1.0
25 clock-names:
27 - const: ref_clk
35 - compatible
[all …]
H A Daltera-pr-ip.txt4 - compatible : should contain "altr,a10-pr-ip"
5 - reg : base address and size for memory mapped io.
9 fpga_mgr: fpga-mgr@ff20c000 {
10 compatible = "altr,a10-pr-ip";
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dintel,stratix10-svc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
11 - Mahesh Rao <mahesh.rao@altera.com>
14 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
15 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
18 configuration data from that location and perform the FPGA configuration.
28 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
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/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cell
[all...]
/freebsd/sys/arm64/intel/
H A Dstratix10-soc-fpga-mgr.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2019-2024 Ruslan Bukin <br@bsdpad.com>
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
34 * Intel Stratix 10 FPGA Manager.
36 * FPGA Programming Example:
57 #include <arm64/intel/stratix10-svc.h>
84 sc = dev->si_drv1; in fpga_open()
86 sx_xlock(&sc->sx); in fpga_open()
87 if (sc->opened) { in fpga_open()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dversal-net.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal-net";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 u-boot {
22 compatible = "u-boot,config";
23 bootscr-address = /bits/ 64 <0x20000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 /delete-node/ &adsp_mem;
21 /delete-node/ &audio_mem;
22 /delete-node/ &cont_splash_mem;
23 /delete-node/ &mba_mem;
24 /delete-node/ &mpss_mem;
25 /delete-node/ &peripheral_region;
[all …]

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