1*c66ec88fSEmmanuel VadotLattice iCE40 FPGA Manager 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible: Should contain "lattice,ice40-fpga-mgr" 5*c66ec88fSEmmanuel Vadot- reg: SPI chip select 6*c66ec88fSEmmanuel Vadot- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) 7*c66ec88fSEmmanuel Vadot- cdone-gpios: GPIO input connected to CDONE pin 8*c66ec88fSEmmanuel Vadot- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note 9*c66ec88fSEmmanuel Vadot that unless the GPIO is held low during startup, the 10*c66ec88fSEmmanuel Vadot FPGA will enter Master SPI mode and drive SCK with a 11*c66ec88fSEmmanuel Vadot clock signal potentially jamming other devices on the 12*c66ec88fSEmmanuel Vadot bus until the firmware is loaded. 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel VadotExample: 15*c66ec88fSEmmanuel Vadot fpga: fpga@0 { 16*c66ec88fSEmmanuel Vadot compatible = "lattice,ice40-fpga-mgr"; 17*c66ec88fSEmmanuel Vadot reg = <0>; 18*c66ec88fSEmmanuel Vadot spi-max-frequency = <1000000>; 19*c66ec88fSEmmanuel Vadot cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 20*c66ec88fSEmmanuel Vadot reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; 21*c66ec88fSEmmanuel Vadot }; 22