1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2019-2024 Ruslan Bukin <br@bsdpad.com>
8  * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
34  * Intel Stratix 10 FPGA Manager.
36  * FPGA Programming Example:
57 #include <arm64/intel/stratix10-svc.h>
84 	sc = dev->si_drv1;  in fpga_open()
86 	sx_xlock(&sc->sx);  in fpga_open()
87 	if (sc->opened) {  in fpga_open()
88 		sx_xunlock(&sc->sx);  in fpga_open()
92 	err = s10_svc_allocate_memory(sc->s10_svc_dev,  in fpga_open()
93 	    &sc->mem, SVC_BUF_SIZE);  in fpga_open()
95 		sx_xunlock(&sc->sx);  in fpga_open()
101 	if (dev == sc->mgr_cdev_partial)  in fpga_open()
103 	ret = s10_svc_send(sc->s10_svc_dev, &msg);  in fpga_open()
105 		sx_xunlock(&sc->sx);  in fpga_open()
109 	sc->opened = 1;  in fpga_open()
110 	sx_xunlock(&sc->sx);  in fpga_open()
122 	sc = dev->si_drv1;  in fpga_submit()
126 	msg.payload = (void *)sc->mem.paddr;  in fpga_submit()
127 	msg.payload_length = sc->mem.fill;  in fpga_submit()
128 	ret = s10_svc_send(sc->s10_svc_dev, &msg);  in fpga_submit()
130 		device_printf(sc->dev, "Failed to submit data\n");  in fpga_submit()
131 		s10_svc_free_memory(sc->s10_svc_dev, &sc->mem);  in fpga_submit()
132 		sc->opened = 0;  in fpga_submit()
139 	ret = s10_svc_send(sc->s10_svc_dev, &msg);  in fpga_submit()
141 		device_printf(sc->dev, "Can't claim buffer back.\n");  in fpga_submit()
155 	sc = dev->si_drv1;  in fpga_write()
157 	sx_xlock(&sc->sx);  in fpga_write()
158 	if (sc->opened == 0) {  in fpga_write()
160 		sx_xunlock(&sc->sx);  in fpga_write()
164 	while (uio->uio_resid > 0) {  in fpga_write()
165 		addr = sc->mem.vaddr + sc->mem.fill;  in fpga_write()
166 		amnt = MIN(uio->uio_resid, (SVC_BUF_SIZE - sc->mem.fill));  in fpga_write()
169 			device_printf(sc->dev, "uiomove returned error %d\n",  in fpga_write()
173 		sc->mem.fill += amnt;  in fpga_write()
174 		if (sc->mem.fill == SVC_BUF_SIZE) {  in fpga_write()
177 				sx_xunlock(&sc->sx);  in fpga_write()
180 			sc->mem.fill = 0;  in fpga_write()
184 	sx_xunlock(&sc->sx);  in fpga_write()
196 	sc = dev->si_drv1;  in fpga_close()
198 	sx_xlock(&sc->sx);  in fpga_close()
199 	if (sc->opened == 0) {  in fpga_close()
201 		sx_xunlock(&sc->sx);  in fpga_close()
205 	if (sc->mem.fill > 0) {  in fpga_close()
208 			sx_xunlock(&sc->sx);  in fpga_close()
211 		sc->mem.fill = 0;  in fpga_close()
214 	s10_svc_free_memory(sc->s10_svc_dev, &sc->mem);  in fpga_close()
215 	sc->opened = 0;  in fpga_close()
216 	sx_xunlock(&sc->sx);  in fpga_close()
235 	.d_name =	"FPGA Manager",
245 	if (!ofw_bus_is_compatible(dev, "intel,stratix10-soc-fpga-mgr"))  in fpgamgr_s10_probe()
248 	device_set_desc(dev, "Stratix 10 SOC FPGA Manager");  in fpgamgr_s10_probe()
260 	sc->dev = dev;  in fpgamgr_s10_attach()
266 	sc->s10_svc_dev = devclass_get_device(dc, 0);  in fpgamgr_s10_attach()
267 	if (sc->s10_svc_dev == NULL)  in fpgamgr_s10_attach()
270 	sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,  in fpgamgr_s10_attach()
271 	    0600, "fpga%d", device_get_unit(sc->dev));  in fpgamgr_s10_attach()
272 	if (sc->mgr_cdev == NULL) {  in fpgamgr_s10_attach()
277 	sc->mgr_cdev_partial = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,  in fpgamgr_s10_attach()
278 	    0600, "fpga_partial%d", device_get_unit(sc->dev));  in fpgamgr_s10_attach()
279 	if (sc->mgr_cdev_partial == NULL) {  in fpgamgr_s10_attach()
284 	sx_init(&sc->sx, "s10 fpga");  in fpgamgr_s10_attach()
286 	sc->mgr_cdev->si_drv1 = sc;  in fpgamgr_s10_attach()
287 	sc->mgr_cdev_partial->si_drv1 = sc;  in fpgamgr_s10_attach()
299 	destroy_dev(sc->mgr_cdev);  in fpgamgr_s10_detach()
300 	destroy_dev(sc->mgr_cdev_partial);  in fpgamgr_s10_detach()
302 	sx_destroy(&sc->sx);  in fpgamgr_s10_detach()