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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsmsc911x.txt1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
[all …]
H A Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
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/freebsd/share/man/man4/
H A Dxl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
57 and "tornado" bus-master Etherlink XL chips.
59 The Etherlink XL chips support built-in 10baseT, 10base2 and 10base5
60 transceivers as well as an MII bus for externally attached PHY
63 NS 83840A 10/100 PHY for 10/100 Mbps support in full or half-duplex.
64 The 3c905B adapters have built-in autonegotiation logic mapped onto
67 adapters such as the 3c905-TX and 3c905B-TX are capable of 10 or
75 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
[all …]
H A Dstge.440 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
57 The Sundance/Tamarack TC9021 is found on the D-Link DGE-550T
59 It uses an external PHY or an external 10-bit interface.
65 receive interrupt moderation mechanism as well as a 64-bit
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
102 .Cm full-duplex
104 .Cm half-duplex
[all …]
H A Dre.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
67 features, and use a descriptor-based DMA mechanism.
71 The 8139C+ is a single-chip solution combining both a 10/100 MAC and PHY.
72 The 8169 is a 10/100/1000 MAC only, requiring a GMII or TBI external PHY.
73 The 816xS, 811xS, 8168 and 8111 are single-chip devices containing both a
74 10/100/1000 MAC and 10/100/1000 copper PHY.
76 in both 32-bit PCI and 64-bit PCI models.
78 embedded LAN-on-motherboard applications.
[all …]
H A Dvge.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
59 The VT6120/VT6122 is a 33/66MHz 64-bit PCI device which combines a tri-speed
60 MAC with an integrated 10/100/1000 copper PHY.
61 (Some older cards use an external PHY.)
65 as well as VLAN filtering, a 64-entry CAM filter and a 64-entry VLAN filter,
66 64-bit multicast hash filter, 4 separate transmit DMA queues, flow control
93 .Bl -tag -width ".Cm 10baseT/UTP"
105 .Cm full-duplex
[all …]
H A Dsis.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
63 The SiS 900 is a 100Mbps Ethernet MAC and MII-compliant transceiver
68 that it has no internal PHY, requiring instead an external transceiver
70 The SiS 900 and SiS 7016 both have a 128-bit multicast hash filter
73 The NS DP83815 is also a 100Mbps Ethernet MAC with integrated PHY.
81 .Bl -tag -width 10baseTXUTP
93 .Sq full-duplex
95 .Sq half-duplex
[all …]
H A Drl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
60 descriptor-based data transfer mechanism.
72 whereas the 8129 uses an external PHY via an MII bus.
85 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
89 supported if the PHY chip attached to the RealTek controller
100 .Ar full-duplex
102 .Ar half-duplex
109 .Ar full-duplex
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_x550.c3 Copyright (c) 2001-2020, Intel Corporation
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
55 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_X550()
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_X550()
62 mac->ops.dmac_config = ixgbe_dmac_config_X550; in ixgbe_init_ops_X550()
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; in ixgbe_init_ops_X550()
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; in ixgbe_init_ops_X550()
65 mac->ops.setup_eee = NULL; in ixgbe_init_ops_X550()
66 mac->ops.set_source_address_pruning = in ixgbe_init_ops_X550()
68 mac->ops.set_ethertype_anti_spoofing = in ixgbe_init_ops_X550()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The SROM controller can be used to attach external peripherals. In this case
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
35 <bank-number> 0 <parent address of bank> <size>
[all …]
/freebsd/sys/dev/bxe/
H A Dbxe_elink.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
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/freebsd/sys/dev/usb/net/
H A Dif_udavreg.h3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the name of the author nor the names of any co-contributors
58 #define UDAV_NCR_EXT_PHY (1<<7) /* Select External PHY */
60 #define UDAV_NCR_FCOL (1<<4) /* Force Collision Mode */
61 #define UDAV_NCR_FDX (1<<3) /* Full-Duplex Mode (RO on Int. PHY) */
79 #define UDAV_RSR_RWTO (1<<4) /* Receive Watchdog Time-Out */
88 #define UDAV_EPCR 0x0b /* EEPROM & PHY Control Register */
91 #define UDAV_EPCR_EPOS (1<<3) /* EEPROM or PHY Operation Select */
92 #define UDAV_EPCR_ERPRR (1<<2) /* EEPROM/PHY Register Read Command */
[all …]
H A Dif_udav.c3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the name of the author nor the names of any co-contributors
36 * DM9601(DAVICOM USB to Ethernet MAC Controller with Integrated 10/100 PHY)
38 * http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf
44 * External PHYs
175 /* Corega USB-TXC */
239 udav_csr_read(sc, UDAV_PAR, ue->ue_eaddr, ETHER_ADDR_LEN); in udav_attach_post()
247 if (uaa->usb_mode != USB_MODE_HOST) in udav_probe()
249 if (uaa->info.bConfigIndex != UDAV_CONFIG_INDEX) in udav_probe()
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82543.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
86 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82543() local
91 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82543()
92 phy->type = e1000_phy_none; in e1000_init_phy_params_82543()
95 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82543()
96 phy->ops.power_down = e1000_power_down_phy_copper; in e1000_init_phy_params_82543()
99 phy->addr = 1; in e1000_init_phy_params_82543()
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82543()
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
390 /* [0x10] 10/100/1000 MAC external configuration */
394 /* [0x18] RGMII external configuration */
398 /* [0x20] 1/2.5/10G MAC external configuration */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
625 * [0x88] SERDES 32-bit interface bit selection
646 /* [0xb0] External SERDES control */
[all …]
/freebsd/sys/dev/le/
H A Dlancereg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp157c-lxa-mc1.dts1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 /dts-v1/;
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
17 model = "Linux Automation MC-1 board";
18 compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
28 compatible = "pwm-backlight";
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
64 /* [0x8] Force init reset. */
66 /* [0xc] Force init reset per DECEI mode. */
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-evb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/pwm/pwm.h>
13 adc-keys {
14 compatible = "adc-keys";
15 io-channels = <&saradc 1>;
16 io-channel-names = "buttons";
17 keyup-threshold-microvolt = <1800000>;
19 button-up {
22 press-threshold-microvolt = <100000>;
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_psgmii.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 * Routines that control the ess-psgmii block - the interconnect
77 * between the ess-switch and the external multi-port PHY
85 bus_space_write_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
87 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
88 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE); in ar40xx_hw_psgmii_reg_write()
96 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
97 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ); in ar40xx_hw_psgmii_reg_read()
98 ret = bus_space_read_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
12 compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
20 compatible = "pwm-backlight";
21 brightness-levels = <
54 default-brightness-leve
[all...]
/freebsd/sys/dev/smc/
H A Dif_smcreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 #define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */
41 #define TCR_FORCOL 0x0004 /* Force a collision */
97 /* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
99 #define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */
100 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
108 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */
116 #define CR_EXT_PHY 0x0200 /* Enable/disable external PHY */
/freebsd/sys/dev/mii/
H A De1000phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
41 * 1000baseSX PHY.
43 * Jung-uk Kim <jkim@niksun.com>
140 (sc->mii_flags & MIIF_MACPRIV0) != 0) in e1000phy_attach()
141 sc->mii_flags |= MIIF_PHYPRIV0; in e1000phy_attach()
143 switch (sc->mii_mpd_model) { in e1000phy_attach()
147 sc->mii_flags |= MIIF_HAVEFIBER; in e1000phy_attach()
152 * Some 88E1149 PHY's page select is initialized to in e1000phy_attach()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-mba6.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-binding
[all...]

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