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/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dbase.c44 nvkm_runl_foreach(runl, engine->subdev.device->fifo) { in nvkm_fifo_ctxsw_in_progress()
55 nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags) in nvkm_fifo_pause() argument
57 return fifo->func->pause(fifo, flags); in nvkm_fifo_pause()
61 nvkm_fifo_start(struct nvkm_fifo *fifo, unsigned long *flags) in nvkm_fifo_start() argument
63 return fifo->func->start(fifo, flags); in nvkm_fifo_start()
67 nvkm_fifo_fault(struct nvkm_fifo *fifo, struct nvkm_fault_data *info) in nvkm_fifo_fault() argument
69 return fifo->func->mmu_fault->recover(fifo, info); in nvkm_fifo_fault()
76 struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); in nvkm_fifo_class_new() local
78 if (oclass->engn == &fifo->func->cgrp.user) in nvkm_fifo_class_new()
79 return nvkm_ucgrp_new(fifo, oclass, argv, argc, pobject); in nvkm_fifo_class_new()
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/linux/sound/soc/meson/
H A Daxg-fifo.c17 #include "axg-fifo.h"
21 * capture frontend DAI. The logic behind this two types of fifo is very
68 static void __dma_enable(struct axg_fifo *fifo, bool enable) in __dma_enable() argument
70 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
77 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_trigger() local
83 __dma_enable(fifo, true); in axg_fifo_pcm_trigger()
88 __dma_enable(fifo, false); in axg_fifo_pcm_trigger()
101 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_pointer() local
105 regmap_read(fifo->map, FIFO_STATUS2, &addr); in axg_fifo_pcm_pointer()
116 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_hw_params() local
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H A Daiu-fifo.c13 #include "aiu-fifo.h"
37 struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai); in aiu_fifo_pointer() local
41 addr = snd_soc_component_read(component, fifo->mem_offset + AIU_MEM_RD); in aiu_fifo_pointer()
49 struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai); in aiu_fifo_enable() local
54 fifo->mem_offset + AIU_MEM_CONTROL, in aiu_fifo_enable()
83 struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai); in aiu_fifo_prepare() local
86 fifo->mem_offset + AIU_MEM_CONTROL, in aiu_fifo_prepare()
90 fifo->mem_offset + AIU_MEM_CONTROL, in aiu_fifo_prepare()
101 struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai); in aiu_fifo_hw_params() local
104 /* Setup the fifo boundaries */ in aiu_fifo_hw_params()
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/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo.c38 /* Virtual devices sharing the TM FIFO. */
76 * @fifo: pointer to the tmfifo structure
95 struct mlxbf_tmfifo *fifo; member
134 * @tx_buf: tx buffer used to buffer data before writing into the FIFO
150 * @fifo: pointer to the tmfifo structure
155 struct mlxbf_tmfifo *fifo; member
180 * @rx_fifo_size: number of entries of the Rx FIFO
181 * @tx_fifo_size: number of entries of the Tx FIFO
211 * @len: payload length in network byte order. Messages sent into the FIFO
245 /* Free vrings of the FIFO device. */
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/linux/drivers/usb/renesas_usbhs/
H A Dfifo.c98 struct usbhs_fifo *fifo);
99 static struct dma_chan *usbhsf_dma_chan_get(struct usbhs_fifo *fifo,
109 struct usbhs_fifo *fifo = usbhs_pipe_to_fifo(pipe); in usbhs_pkt_pop() local
123 if (fifo) in usbhs_pkt_pop()
124 chan = usbhsf_dma_chan_get(fifo, pkt); in usbhs_pkt_pop()
141 if (fifo) in usbhs_pkt_pop()
142 usbhsf_fifo_unselect(pipe, fifo); in usbhs_pkt_pop()
255 * FIFO ctrl
258 struct usbhs_fifo *fifo) in usbhsf_send_terminator() argument
262 usbhs_bset(priv, fifo->ctr, BVAL, BVAL); in usbhsf_send_terminator()
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/linux/drivers/iio/imu/inv_icm42600/
H A Dinv_icm42600_buffer.c21 /* FIFO header: 1 byte */
53 /* FIFO empty */ in inv_icm42600_fifo_decode_packet()
106 if (st->fifo.en & INV_ICM42600_SENSOR_GYRO) in inv_icm42600_buffer_update_fifo_period()
111 if (st->fifo.en & INV_ICM42600_SENSOR_ACCEL) in inv_icm42600_buffer_update_fifo_period()
116 st->fifo.period = min(period_gyro, period_accel); in inv_icm42600_buffer_update_fifo_period()
125 /* update only FIFO EN bits */ in inv_icm42600_buffer_set_fifo_en()
143 st->fifo.en = fifo_en; in inv_icm42600_buffer_set_fifo_en()
178 * inv_icm42600_buffer_update_watermark - update watermark FIFO threshold
183 * FIFO watermark threshold is computed based on the required watermark values
196 * to the FIFO frequency. Beware that this is only true because we are not
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/linux/drivers/md/bcache/
H A Dutil.h119 #define fifo_for_each(c, fifo, iter) \ argument
120 for (iter = (fifo)->front; \
121 c = (fifo)->data[iter], iter != (fifo)->back; \
122 iter = (iter + 1) & (fifo)->mask)
124 #define __init_fifo(fifo, gfp) \ argument
127 BUG_ON(!(fifo)->size); \
129 _allocated_size = roundup_pow_of_two((fifo)->size + 1); \
130 _bytes = _allocated_size * sizeof(*(fifo)->data); \
132 (fifo)->mask = _allocated_size - 1; \
133 (fifo)->front = (fifo)->back = 0; \
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/linux/drivers/iio/imu/inv_icm45600/
H A Dinv_icm45600_buffer.c24 /* FIFO header: 1 byte */
57 /* FIFO extended header */ in inv_icm45600_fifo_decode_packet()
106 if (st->fifo.en & INV_ICM45600_SENSOR_GYRO) in inv_icm45600_buffer_update_fifo_period()
111 if (st->fifo.en & INV_ICM45600_SENSOR_ACCEL) in inv_icm45600_buffer_update_fifo_period()
116 st->fifo.period = min(period_gyro, period_accel); in inv_icm45600_buffer_update_fifo_period()
134 st->fifo.en = fifo_en; in inv_icm45600_buffer_set_fifo_en()
145 /* Keep 20ms for processing FIFO.*/ in inv_icm45600_wm_truncate()
157 * inv_icm45600_buffer_update_watermark - update watermark FIFO threshold
160 * FIFO watermark threshold is computed based on the required watermark values
173 * to the FIFO frequency.
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/linux/drivers/usb/fotg210/
H A Dfotg210-udc.h47 /* Cx configuration and FIFO Empty Status register(0x120) */
49 #define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo)) argument
78 #define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo))) argument
87 #define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2) argument
111 #define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2)) argument
112 #define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2)) argument
113 #define DISGR1_IN_INT(fifo) (1 << 16 << (fifo)) argument
165 /* Device FIFO Map Register (0x1A8) */
167 #define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8) argument
168 #define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8) argument
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/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_mbx.c7 * fm10k_fifo_init - Initialize a message FIFO
8 * @fifo: pointer to FIFO
9 * @buffer: pointer to memory to be used to store FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
12 static void fm10k_fifo_init(struct fm10k_mbx_fifo *fifo, u32 *buffer, u16 size) in fm10k_fifo_init() argument
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
17 fifo->tail = 0; in fm10k_fifo_init()
21 * fm10k_fifo_used - Retrieve used space in FIFO
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/linux/arch/powerpc/platforms/powernv/
H A Dvas-fault.c21 * The maximum FIFO size for fault window can be 8MB
22 * (VAS_RX_FIFO_SIZE_MAX). Using 4MB FIFO since each VAS
24 * 8MB FIFO can be used if expects more faults for each VAS
32 unsigned long *fifo = entry; in dump_fifo() local
35 pr_err("Fault fifo size %d, Max crbs %d\n", vinst->fault_fifo_size, in dump_fifo()
38 /* Dump 10 CRB entries or until end of FIFO */ in dump_fifo()
39 pr_err("Fault FIFO Dump:\n"); in dump_fifo()
40 for (i = 0; i < 10*(CRB_SIZE/8) && fifo < end; i += 4, fifo += 4) { in dump_fifo()
42 i, fifo, *fifo, *(fifo+1), *(fifo+2), *(fifo+3)); in dump_fifo()
47 * Process valid CRBs in fault FIFO.
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/linux/drivers/spi/
H A Dspi-mpc512x-psc.c55 struct mpc512x_psc_fifo __iomem *fifo; member
147 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; in mpc512x_psc_spi_transfer_rxtx() local
167 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); in mpc512x_psc_spi_transfer_rxtx()
169 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz)); in mpc512x_psc_spi_transfer_rxtx()
170 fifosz -= in_be32(&fifo->rxcnt) + 1; in mpc512x_psc_spi_transfer_rxtx()
174 /* fill the TX FIFO */ in mpc512x_psc_spi_transfer_rxtx()
178 setbits32(&fifo->txcmd, in mpc512x_psc_spi_transfer_rxtx()
180 out_8(&fifo->txdata_8, data); in mpc512x_psc_spi_transfer_rxtx()
184 /* have the ISR trigger when the TX FIFO is empty */ in mpc512x_psc_spi_transfer_rxtx()
186 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); in mpc512x_psc_spi_transfer_rxtx()
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5121-psc.txt8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
19 PSC FIFO Controller and b is a field that represents an
23 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
24 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
30 for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
35 fsl,mpc512x-psc-fifo node
39 - compatible : Should be "fsl,<soc>-psc-fifo"
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
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/linux/sound/arm/
H A Dpxa2xx-ac97-regs.h10 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
11 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
14 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
15 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
18 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
19 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
38 #define POSR_FIFOE (1 << 4) /* FIFO error */
39 #define POSR_FSR (1 << 2) /* FIFO Service Request */
42 #define PISR_FIFOE (1 << 4) /* FIFO error */
44 #define PISR_FSR (1 << 2) /* FIFO Service Request */
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H A Daaci.h19 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
20 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
41 #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
43 #define AACI_DR1 0x090 /* data read/written fifo 1 */
44 #define AACI_DR2 0x0b0 /* data read/written fifo 2 */
45 #define AACI_DR3 0x0d0 /* data read/written fifo 3 */
46 #define AACI_DR4 0x0f0 /* data read/written fifo 4 */
49 * TX/RX fifo control register (CR). P48
51 #define CR_FEN (1 << 16) /* fifo enable */
74 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
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/linux/drivers/mailbox/
H A Domap-mailbox.c105 /* Mailbox FIFO handle functions */
108 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read() local
110 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
115 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_write() local
117 mbox_write_reg(mbox->parent, msg, fifo->msg); in mbox_fifo_write()
122 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_empty() local
124 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); in mbox_fifo_empty()
129 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_full() local
131 return mbox_read_reg(mbox->parent, fifo->fifo_stat); in mbox_fifo_full()
137 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? in ack_mbox_irq() local
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/linux/samples/kfifo/
H A Ddma-example.c3 * Sample fifo dma implementation
15 * This module shows how to handle fifo dma operations.
18 /* fifo size in elements (bytes) */
21 static struct kfifo fifo; variable
30 printk(KERN_INFO "DMA fifo test start\n"); in example_init()
32 if (kfifo_alloc(&fifo, FIFO_SIZE, GFP_KERNEL)) { in example_init()
37 printk(KERN_INFO "queue size: %u\n", kfifo_size(&fifo)); in example_init()
39 kfifo_in(&fifo, "test", 4); in example_init()
42 kfifo_put(&fifo, i); in example_init()
45 kfifo_skip(&fifo); in example_init()
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H A Dbytestream-example.c15 * This module shows how to create a byte stream fifo.
18 /* fifo size in elements (bytes) */
22 #define PROC_FIFO "bytestream-fifo"
31 * define DYNAMIC in this example for a dynamically allocated fifo.
33 * Otherwise the fifo storage will be a part of the fifo structure.
58 printk(KERN_INFO "byte stream fifo test start\n"); in testfunc()
60 /* put string into the fifo */ in testfunc()
63 /* put values into the fifo */ in testfunc()
68 printk(KERN_INFO "fifo len: %u\n", kfifo_len(&test)); in testfunc()
70 /* get max of 5 bytes from the fifo */ in testfunc()
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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_cmd.c39 const struct vmw_fifo_state *fifo = dev_priv->fifo; in vmw_supports_3d() local
65 ((fifo->capabilities & in vmw_supports_3d()
99 struct vmw_fifo_state *fifo; in vmw_fifo_create() local
106 fifo = kzalloc_obj(*fifo); in vmw_fifo_create()
107 if (!fifo) in vmw_fifo_create()
109 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; in vmw_fifo_create()
110 fifo->static_buffer = vmalloc(fifo->static_buffer_size); in vmw_fifo_create()
111 if (unlikely(fifo->static_buffer == NULL)) { in vmw_fifo_create()
112 kfree(fifo); in vmw_fifo_create()
116 fifo->dynamic_buffer = NULL; in vmw_fifo_create()
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/linux/include/linux/
H A Dpxa2xx_ssp.h62 #define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
66 #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
70 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
71 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
78 #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */
79 #define SSSR_RNE BIT(3) /* Receive FIFO Not Empty */
81 #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
82 #define SSSR_RFS BIT(6) /* Receive FIFO Service Request */
83 #define SSSR_ROR BIT(7) /* Receive FIFO Overrun */
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/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
18 "xlnx,axi-fifo-mm-s-4.1"
19 "xlnx,axi-fifo-mm-s-4.2"
20 "xlnx,axi-fifo-mm-s-4.3"
40 - xlnx,rx-fifo-depth: Depth of RX FIFO in words
41 - xlnx,rx-fifo-pe-threshold: RX programmable empty interrupt threshold
43 - xlnx,rx-fifo-pf-threshold: RX programmable full interrupt threshold
48 - xlnx,tx-fifo-depth: Depth of TX FIFO in words
49 - xlnx,tx-fifo-pe-threshold: TX programmable empty interrupt threshold
51 - xlnx,tx-fifo-pf-threshold: TX programmable full interrupt threshold
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/linux/drivers/char/xillybus/
H A Dxillyusb.c8 * a pipe between a hardware FIFO in the programmable logic and a device
76 int fill; /* Number of bytes in the FIFO */
107 struct xillyfifo fifo; member
219 * calls to each on the same FIFO is not allowed) however it's OK to have
220 * threads calling each of the two functions once on the same FIFO, and
224 static int fifo_write(struct xillyfifo *fifo, in fifo_write() argument
231 unsigned int writepos = fifo->writepos; in fifo_write()
232 unsigned int writebuf = fifo->writebuf; in fifo_write()
236 nmax = fifo->size - READ_ONCE(fifo->fill); in fifo_write()
239 unsigned int nrail = fifo->bufsize - writepos; in fifo_write()
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/linux/sound/soc/tegra/
H A Dtegra20_spdif.h75 /* Interrupt when RX user FIFO attention level is reached */
78 /* Interrupt when TX user FIFO attention level is reached */
81 /* Interrupt when RX data FIFO attention level is reached */
84 /* Interrupt when TX data FIFO attention level is reached */
152 * TX User data FIFO busy.
154 * there's data in the TX user FIFO. This bit is deassert when either,
156 * (b) there's no data left in the TX user FIFO.
160 /* TX FIFO Underrun error status */
163 /* RX FIFO Overrun error status */
183 * RX User FIFO Statu
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/linux/drivers/tty/serial/
H A Datmel_serial.h36 #define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */
37 #define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */
38 #define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */
39 #define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */
40 #define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */
138 #define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */
144 #define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */
145 #define ATMEL_US_TXFTHRES(thr) FIELD_PREP(GENMASK(13, 8), (thr)) /* TX FIFO Threshold */
146 #define ATMEL_US_RXFTHRES(thr) FIELD_PREP(GENMASK(21, 16), (thr)) /* RX FIFO Threshold */
147 #define ATMEL_US_RXFTHRES2(thr) FIELD_PREP(GENMASK(29, 24), (thr)) /* RX FIFO Threshold2 */
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dfifo.c22 #include <engine/fifo/priv.h>
23 #include <engine/fifo/cgrp.h>
24 #include <engine/fifo/chan.h>
25 #include <engine/fifo/chid.h>
26 #include <engine/fifo/runl.h>
38 #include "nvrm/fifo.h"
46 return gsp->rm->gpu->fifo.chan.doorbell_handle(chan); in r535_chan_doorbell_handle()
62 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in r535_chan_ramfc_clear() local
66 dma_free_coherent(fifo->engine.subdev.device->dev, fifo->rm.mthdbuf_size, in r535_chan_ramfc_clear()
81 struct nvkm_fifo *fifo = gsp->subdev.device->fifo; in r535_chan_alloc() local
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