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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5410-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5410 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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H A Dsamsung,exynos-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/exynos-audss-clk.h header.
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5410 SoC device tree source
8 * Samsung Exynos5410 SoC device nodes are listed in this file.
9 * Exynos5410 based board files can include this file and provide
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5410", "samsung,exynos5";
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
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H A Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include "exynos5410.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
13 model = "Samsung SMDK5410 board based on Exynos5410";
14 compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
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H A Dexynos5410-odroidxu.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include "exynos5410.dtsi"
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos54xx-odroidxu-leds.dtsi"
20 compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
34 stdout-path = "serial2:115200n8";
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H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
9 * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
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/linux/drivers/clk/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
42 Support for the clock controller present on the Samsung
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H A Dclk-exynos5410.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5410 SoC.
9 #include <dt-bindings/clock/exynos5410.h>
11 #include <linux/clk-provider.h>
59 /* NOTE: Must be equal to the last clock ID increased by one */
269 /* register exynos5410 clocks */
279 pr_debug("Exynos5410: clock setup completed.\n"); in exynos5410_clk_init()
281 CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Samsung Clock specific Makefile
6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o
8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o
9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o
10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o
11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o
12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
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H A Dclk-exynos-clkout.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Clock driver for Exynos clock output
11 #include <linux/clk-provider.h>
20 #define DRV_NAME "exynos-clkout"
55 .compatible = "samsung,exynos3250-pmu",
58 .compatible = "samsung,exynos4210-pmu",
61 .compatible = "samsung,exynos4212-pmu",
64 .compatible = "samsung,exynos4412-pmu",
67 .compatible = "samsung,exynos5250-pmu",
70 .compatible = "samsung,exynos5410-pmu",
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H A Dclk-exynos-audss.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Audio Subsystem Clock Controller.
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/exynos-audss-clk.h>
24 * On Exynos5420 this will be a clock which has to be enabled before any
27 * On other platforms this will be -ENODEV.
69 .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
74 .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
86 .compatible = "samsung,exynos4210-audss-clock",
89 .compatible = "samsung,exynos5250-audss-clock",
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
35 /* Retention control for S5PV210 are located at the end of clock controller */
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
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H A Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
32 #include "pinctrl-samsung.h"
42 { "samsung,pin-pud", PINCFG_TYPE_PUD },
43 { "samsung,pin-drv", PINCFG_TYPE_DRV },
44 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
45 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
46 { "samsung,pin-val", PINCFG_TYPE_DAT },
53 return pmx->nr_groups; in samsung_get_group_count()
61 return pmx->pin_groups[group].name; in samsung_get_group_name()
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/linux/arch/arm/mach-exynos/
H A Dexynos.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
15 #include <linux/soc/samsung/exynos-regs-pmu.h>
18 #include <asm/hardware/cache-l2x0.h>
33 .id = -1,
52 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") { in exynos_sysram_init()
64 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") { in exynos_sysram_init()
80 if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid")) in exynos_fdt_map_chipid()
88 iodesc.length = be32_to_cpu(reg[1]) - 1; in exynos_fdt_map_chipid()
114 * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down
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/linux/drivers/i2c/busses/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
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