Lines Matching +full:exynos5410 +full:- +full:clock

1 // SPDX-License-Identifier: GPL-2.0-only
6  * Common Clock Framework support for Audio Subsystem Clock Controller.
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/exynos-audss-clk.h>
24  * On Exynos5420 this will be a clock which has to be enabled before any
27  * On other platforms this will be -ENODEV.
69 	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
74 	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
86 		.compatible	= "samsung,exynos4210-audss-clock",
89 		.compatible	= "samsung,exynos5250-audss-clock",
92 		.compatible	= "samsung,exynos5410-audss-clock",
95 		.compatible	= "samsung,exynos5420-audss-clock",
107 		if (!IS_ERR(clk_data->hws[i]))  in exynos_audss_clk_teardown()
108 			clk_hw_unregister_mux(clk_data->hws[i]);  in exynos_audss_clk_teardown()
112 		if (!IS_ERR(clk_data->hws[i]))  in exynos_audss_clk_teardown()
113 			clk_hw_unregister_divider(clk_data->hws[i]);  in exynos_audss_clk_teardown()
116 	for (; i < clk_data->num; i++) {  in exynos_audss_clk_teardown()
117 		if (!IS_ERR(clk_data->hws[i]))  in exynos_audss_clk_teardown()
118 			clk_hw_unregister_gate(clk_data->hws[i]);  in exynos_audss_clk_teardown()
131 	struct device *dev = &pdev->dev;  in exynos_audss_clk_probe()
134 	variant = of_device_get_match_data(&pdev->dev);  in exynos_audss_clk_probe()
136 		return -EINVAL;  in exynos_audss_clk_probe()
142 	epll = ERR_PTR(-ENODEV);  in exynos_audss_clk_probe()
149 		return -ENOMEM;  in exynos_audss_clk_probe()
151 	clk_data->num = variant->num_clks;  in exynos_audss_clk_probe()
152 	clk_table = clk_data->hws;  in exynos_audss_clk_probe()
161 		if (variant->enable_epll) {  in exynos_audss_clk_probe()
167 					"failed to prepare the epll clock\n");  in exynos_audss_clk_probe()
174 	 * Enable runtime PM here to allow the clock core using runtime PM  in exynos_audss_clk_probe()
177 	 * clock core from runtime suspending the device.  in exynos_audss_clk_probe()
234 	if (variant->has_adma_clk) {  in exynos_audss_clk_probe()
240 	for (i = 0; i < clk_data->num; i++) {  in exynos_audss_clk_probe()
242 			dev_err(dev, "failed to register clock %d\n", i);  in exynos_audss_clk_probe()
248 	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,  in exynos_audss_clk_probe()
251 		dev_err(dev, "failed to add clock provider\n");  in exynos_audss_clk_probe()
272 	of_clk_del_provider(pdev->dev.of_node);  in exynos_audss_clk_remove()
275 	pm_runtime_disable(&pdev->dev);  in exynos_audss_clk_remove()
290 		.name = "exynos-audss-clk",
301 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
303 MODULE_ALIAS("platform:exynos-audss-clk");