Lines Matching +full:exynos5410 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5410 SoC device tree source
8 * Samsung Exynos5410 SoC device nodes are listed in this file.
9 * Exynos5410 based board files can include this file and provide
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5410", "samsung,exynos5";
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
44 clock-frequency = <1600000000>;
49 compatible = "arm,cortex-a15";
51 clock-frequency = <1600000000>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1600000000>;
63 compatible = "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <1>;
68 pmu_system_controller: system-controller@10040000 {
69 compatible = "samsung,exynos5410-pmu", "syscon";
71 clock-names = "clkout16";
73 #clock-cells = <1>;
76 clock: clock-controller@10010000 { label
77 compatible = "samsung,exynos5410-clock";
79 #clock-cells = <1>;
82 clock_audss: audss-clock-controller@3810000 {
83 compatible = "samsung,exynos5410-audss-clock";
85 #clock-cells = <1>;
86 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
87 clock-names = "pll_ref", "pll_in";
91 compatible = "samsung,exynos5420-tmu";
94 clocks = <&clock CLK_TMU>;
95 clock-names = "tmu_apbif";
96 #thermal-sensor-cells = <0>;
100 compatible = "samsung,exynos5420-tmu";
103 clocks = <&clock CLK_TMU>;
104 clock-names = "tmu_apbif";
105 #thermal-sensor-cells = <0>;
109 compatible = "samsung,exynos5420-tmu";
112 clocks = <&clock CLK_TMU>;
113 clock-names = "tmu_apbif";
114 #thermal-sensor-cells = <0>;
118 compatible = "samsung,exynos5420-tmu";
121 clocks = <&clock CLK_TMU>;
122 clock-names = "tmu_apbif";
123 #thermal-sensor-cells = <0>;
127 compatible = "samsung,exynos5250-dw-mshc";
130 #address-cells = <1>;
131 #size-cells = <0>;
132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
133 clock-names = "biu", "ciu";
134 fifo-depth = <0x80>;
139 compatible = "samsung,exynos5250-dw-mshc";
142 #address-cells = <1>;
143 #size-cells = <0>;
144 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
145 clock-names = "biu", "ciu";
146 fifo-depth = <0x80>;
151 compatible = "samsung,exynos5250-dw-mshc";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
157 clock-names = "biu", "ciu";
158 fifo-depth = <0x80>;
163 compatible = "samsung,exynos5410-pinctrl";
167 wakeup-interrupt-controller {
168 compatible = "samsung,exynos4210-wakeup-eint";
169 interrupt-parent = <&gic>;
175 compatible = "samsung,exynos5410-pinctrl";
181 compatible = "samsung,exynos5410-pinctrl";
187 compatible = "samsung,exynos5410-pinctrl";
192 pdma0: dma-controller@121a0000 {
196 clocks = <&clock CLK_PDMA0>;
197 clock-names = "apb_pclk";
198 #dma-cells = <1>;
201 pdma1: dma-controller@121b0000 {
205 clocks = <&clock CLK_PDMA1>;
206 clock-names = "apb_pclk";
207 #dma-cells = <1>;
211 compatible = "samsung,exynos5420-i2s";
216 dma-names = "tx", "rx", "tx-sec";
220 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
221 #clock-cells = <1>;
222 clock-output-names = "i2s_cdclk0";
223 #sound-dai-cells = <1>;
224 samsung,idma-addr = <0x03000000>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&audi2s0_bus>;
231 thermal-zones {
232 cpu0_thermal: cpu0-thermal {
233 thermal-sensors = <&tmu_cpu0>;
234 #include "exynos5420-trip-points.dtsi"
236 cpu1_thermal: cpu1-thermal {
237 thermal-sensors = <&tmu_cpu1>;
238 #include "exynos5420-trip-points.dtsi"
240 cpu2_thermal: cpu2-thermal {
241 thermal-sensors = <&tmu_cpu2>;
242 #include "exynos5420-trip-points.dtsi"
244 cpu3_thermal: cpu3-thermal {
245 thermal-sensors = <&tmu_cpu3>;
246 #include "exynos5420-trip-points.dtsi"
252 clocks = <&clock CLK_TSADC>;
253 clock-names = "adc";
254 samsung,syscon-phandle = <&pmu_system_controller>;
258 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
263 clocks = <&clock CLK_I2C0>;
264 clock-names = "i2c";
265 pinctrl-names = "default";
266 pinctrl-0 = <&i2c0_bus>;
270 clocks = <&clock CLK_I2C1>;
271 clock-names = "i2c";
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c1_bus>;
277 clocks = <&clock CLK_I2C2>;
278 clock-names = "i2c";
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c2_bus>;
284 clocks = <&clock CLK_I2C3>;
285 clock-names = "i2c";
286 pinctrl-names = "default";
287 pinctrl-0 = <&i2c3_bus>;
291 clocks = <&clock CLK_USI0>;
292 clock-names = "hsi2c";
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c4_hs_bus>;
298 clocks = <&clock CLK_USI1>;
299 clock-names = "hsi2c";
300 pinctrl-names = "default";
301 pinctrl-0 = <&i2c5_hs_bus>;
305 clocks = <&clock CLK_USI2>;
306 clock-names = "hsi2c";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c6_hs_bus>;
312 clocks = <&clock CLK_USI3>;
313 clock-names = "hsi2c";
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c7_hs_bus>;
319 clocks = <&fin_pll>, <&clock CLK_MCT>;
320 clock-names = "fin_pll", "mct";
324 clocks = <&clock CLK_SSS>;
325 clock-names = "secss";
329 clocks = <&clock CLK_PWM>;
330 clock-names = "timers";
334 clocks = <&clock CLK_RTC>;
335 clock-names = "rtc";
340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
341 clock-names = "uart", "clk_uart_baud0";
343 dma-names = "rx", "tx";
347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
348 clock-names = "uart", "clk_uart_baud0";
350 dma-names = "rx", "tx";
354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
355 clock-names = "uart", "clk_uart_baud0";
357 dma-names = "rx", "tx";
361 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
362 clock-names = "uart", "clk_uart_baud0";
364 dma-names = "rx", "tx";
368 clocks = <&clock CLK_SSS>;
369 clock-names = "secss";
373 #address-cells = <2>;
374 #size-cells = <1>;
382 clocks = <&clock CLK_SSS>;
383 clock-names = "secss";
387 clocks = <&clock CLK_USBD300>;
388 clock-names = "usbdrd30";
389 pinctrl-names = "default";
390 pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>;
394 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
395 clock-names = "phy", "ref";
396 samsung,pmu-syscon = <&pmu_system_controller>;
400 clocks = <&clock CLK_USBD301>;
401 clock-names = "usbdrd30";
402 pinctrl-names = "default";
403 pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>;
411 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
412 clock-names = "phy", "ref";
413 samsung,pmu-syscon = <&pmu_system_controller>;
417 clocks = <&clock CLK_USBH20>;
418 clock-names = "usbhost";
422 clocks = <&clock CLK_USBH20>;
423 clock-names = "usbhost";
427 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
428 clock-names = "phy", "ref";
429 samsung,sysreg-phandle = <&sysreg_system_controller>;
430 samsung,pmureg-phandle = <&pmu_system_controller>;
434 clocks = <&clock CLK_WDT>;
435 clock-names = "watchdog";
436 samsung,syscon-phandle = <&pmu_system_controller>;
439 #include "exynos5410-pinctrl.dtsi"
440 #include "exynos-syscon-restart.dtsi"